Semiconductor device having ESD protective transistor

Details Semiconductor device having ESD protective transistor Semiconductor device having ESD protective transistor

2003-02-28

2003-12-30

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S360000

Reexamination Certificate

active

06670678

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a semiconductor integrated circuit (IC) device having an electrostatic discharge (ESD) protection transistor.
BACKGROUND OF THE INVENTION
Advancement of sub-micron integration technologies in the production of integrated circuit (IC) devices has necessitated improvement of ESD resistance property of the ICs. In order to avoid destruction of IC devices by ESD, a protective circuit against ESD (referred to as ESD protective circuit) is provided in the I/O circuit of an IC.
FIG. 1
illustrates a structure of a gate-grounded (GG) NMOS transistor serving as an ESD protection transistor of a conventional IC. As shown in
FIG. 1
, an n
+
drain region and an n
+
source region are formed in the MOS region in a p-type well Pwell formed in a p-type substrate Psub. A source S and a drain D are formed by forming contacts on the respective source and drain regions. A gate G is formed above the channel region which lies between the drain and source regions.
The gate G and the source S are grounded and the drain D is connected to the line to be protected. The p
+
substrate contact region and the contact formed thereon together constitute a substrate contact Csub. The substrate contact Csub is grounded so as to be clamped to the ground potential. Formed between the n
+
drain region and the p
+
substrate contact region is an isolation region Ts for securing a withstand voltage. The isolation region Ts can be a Local Oxidation Silicon (LOCOS) or a Shallow Trench Isolation (STI). The example shown herein utilizes an STI in order to secure a minute isolation width. This SIT has been formed as shallow as possible for ease of fabrication and minimization of manufacturing time of the IC so long as withstanding voltages are secured and inter-element leaks are prevented.
The drain region, p-type well region, and source region of this GG NMOS transistor together form a parasitic bipolar junction transistor BJT (referred to as parasitic BJT). When the drain D is positively charged due to ESD, the charge results in electron-hole pairs in the drain region, which in turn results in a current from an equivalent current source I
1
that flows through the p-type well region Pwell.
FIG. 2
shows a graph of drain voltage Vd versus drain current Id of a typical Vd-Id characteristic. It is seen that the parasitic BJT becomes conducting and enters a snapback region (labeled as ii in
FIG. 2
) as the voltage drop caused by the current flowing from the current source I
1
through the resistance Rw of the p-type well region Pwell exceeds the trigger voltage Vtrig of the parasitic BJT (at point i of FIG.
2
), This causes the GG NMOS channel to become conductive, thereby permitting the drain current to flow from the drain D to the source S, and allowing the charge fed to the drain D to be absorbed by the ground. As a consequence, the device is prevented from being destructed.
The Vd-Id characteristic shown in
FIG. 2
is called transmission line pulsing (TLP) characteristic or snapback characteristic. The magnitude of the trigger voltage Vtrig for triggering the parasitic BJT is important in determining the protection capability of the ESD protection transistor.
Advancement of miniaturization and integration of circuits have led to a large scale IC (LSI) in which a MOS transistor inside the core thereof has a highly doped p-type well region Pwell and reduced resistance. Accordingly, the trigger voltage Vtrig of its TLP characteristic tends to become higher. As a consequence, a parasitic BJT becomes more difficult to operate and losing its ESD capability. When the trigger voltage Vtrig becomes very high that it exceeds the breakdown voltage of the MOS transistor, the MOS transistor can break down and gets destroyed. Hence, it is necessary to hold the trigger voltage Vtrig below the breakdown voltage of the MOS transistor.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an IC having an ESD protection transistor formed in a highly doped well region and yet having an improved TLP characteristic for satisfactory ESD protection of the IC.
In accordance with one aspect of the invention, there is provided an IC having an ESD protection transistor, the ESD protection transistor comprising:
a first conductivity type (referred to as p-type or p) well formed in a p-type substrate;
a second conductivity type (referred to as n-type or n) source region formed in the p-type well;
an n-type drain region formed in the p-type well, away from the source region across a channel region;
a p-type substrate contact region formed in the p-type well and on at least the opposite side of the channel region with respect to the drain region;
a gate formed above, and insulated from, the channel region; and
an insulation trench that extends to a depth beyond the thickness of the p-type well and reaching the p-type substrate, the insulation trench formed between at least the drain region and the substrate contact region.
An IC of the invention has an insulation trench formed between a drain region and a substrate contact region, extending beyond the thickness of the p-type well in which the drain region is formed, to the p-type substrate. This configuration leads to an increase of base resistance of the parasitic BJT, which facilitates an easy rise of the base voltage at the time an electric charge is input to the drain region. Hence, it makes easy for the parasitic BJT of the ESD protection transistor to operate promptly and provide improved ESD protection capability.
The ESD protection capability can be secured by simply increasing only the depth (that is, without increasing the width) of the insulation trench, which has traditionally formed shallow to provide a withstand voltage between the drain region and the substrate contact region. It is thus not necessary to increase the area of the ESD transistor or add any extra process in order to increase the resistance of the parasitic BJT. Thus, the ESD transistor is cost effective.
Since the resistance of the ESD protection transistor can be adjusted by controlling the depth of the insulation trench, desired protective characteristics of the ESD transistor can be easily obtained.
In accordance with another aspect of the invention, there is provided an IC having an ESD protection transistor, the ESD protection transistor comprising:
a p-type well formed on a p-type substrate;
an n-type source region formed in the p-type well;
an n-type drain region formed in the p-type well and away from the source region across a channel region;
a p-type substrate contact region formed in the p-type substrate and on at least the opposite side of the channel region with respect to the drain region;
a gate formed above, and insulated from, the channel region; and
an insulation trench that extends to a depth beyond the thickness of the p-type well, the insulation trench formed between at least the drain region and the substrate contact region.
Since an IC of this embodiment of the invention is provided with a substrate contact formed directly on the p-type substrate, the resistance of the ESD protection transistor is made higher than that of conventional one, thereby successfully suppressing the operational voltage of the parasitic BJT of the ESD protection transistor.
In accordance with another aspect of the invention, there is provided an IC having an ESD protection transistor, said ESD protection transistor comprising:
a first n-type well formed on a p-type substrate;
a second n-type well formed in the first n-type well;
a p-type source region formed in the second n-type well;
a p-type drain region formed in the second n well, away from the source region across a channel region;
an n-type substrate contact region formed in the second n-type well, on at least the opposite side of the channel region with respect to the drain region;
a gate formed above, and insulated from, the channel region; and
an insulation trench that extends to a depth beyond the thickness of the first n-type well and reaching the first n we

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