Semiconductor device having embedded array

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C719S323000, C719S323000

Reexamination Certificate

active

06934919

ABSTRACT:
A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).

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patent: 5617369 (1997-04-01), Tomishima et al.
patent: 5677641 (1997-10-01), Nishio et al.
patent: 5701255 (1997-12-01), Fukui
patent: 6226782 (2001-05-01), Nowak et al.
patent: 8-1948 (1996-01-01), None

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