Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-02
2005-08-02
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06925615
ABSTRACT:
A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).
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patent: 3633268 (1972-01-01), Engbert
patent: 5610831 (1997-03-01), Matsumoto
patent: 5617369 (1997-04-01), Tomishima et al.
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patent: 5798937 (1998-08-01), Bracha et al.
patent: 8-1948 (1996-01-01), None
Kosugi Noboru
Oba Hisayoshi
Tahara Munehiro
Yokota Noboru
Fujitsu Limited
Westerman Hattori Daniels & Adrian LLP
Whitmore Stacy A.
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