Semiconductor device having electric fuse element

Details Semiconductor device having electric fuse element Semiconductor device having electric fuse element

2002-01-08

2004-01-20

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S189050, C327S525000, C327S526000

Reexamination Certificate

active

06680873

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-005561, filed Jan. 12, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to, for example, a semiconductor device and more specifically to an electric fuse circuit that is used for setting an operation of the semiconductor device, setting an address of a redundancy circuit, and the like.
2. Description of the Related Art
A fuse circuit is used for setting an operation of a semiconductor device, an address of a redundancy circuit, and the like. A laser fuse that is blown by a laser beam has been used as the fuse circuit; however, its programming is complicated. When a defective memory cell is detected in a process of testing a semiconductor device, it cannot be replaced with a spare cell at once. After the testing, a wafer is carried to another device and in this device a fuse is blown by a laser beam, thereby replacing the defective memory cell with a spare cell. Thus, it takes time to program the laser fuse.
An electrically programmable electric fuse that is easily programmed is developed.
FIG. 11
shows an example of a general electric fuse circuit.
The electric fuse circuit comprises a voltage generation circuit
101
, a plurality of fuse circuits
102
1
and
102
2
to
102
n
, a first switch circuit
103
, a second switch circuit
104
, a detection circuit
105
, a first common wire
106
, a second common wire
107
, and a pad
108
. The fuse circuits
102
1
and
102
2
to
102
n
and the first and second switch circuits
103
and
104
are provided for each bank of a semiconductor device and used for setting an address of a redundancy circuit.
The voltage generation circuit
101
generates a high voltage VBP of about 9V in response to a program signal PRGM when a fuse element is programmed. The circuit
101
is connected to the first switch circuit
103
through the first common wire
106
.
The first switch circuit
103
includes N-channel MOS transistors N
10
and N
11
, P-channel MOS transistors P
10
and P
11
, a NAND circuit ND
1
, and an inverter circuit IV
1
supplied with an output signal of the NAND circuit ND
1
. The input terminal of the NAND circuit ND
1
is supplied with the program signal PRGM and bank select signal BSS. A connection node between the transistors P
10
and N
10
of the first switch circuit
103
is connected to one end portion of each of the fuse circuits
102
1
and
102
2
to
102
n
.
The fuse circuits
102
2
to
102
n
each have the same arrangement as that of the fuse circuit
102
1
. The fuse circuit
102
1
includes a fuse element FS, N-channel MOS transistors N
1
and N
2
, and a latch circuit LT. The fuse element FS includes, for example, a trench capacitor that is applied to, e.g., a dynamic RAM. The fuse element FS increases in resistance before programming and decreases in resistance after programming. The transistor N
1
is a barrier transistor for protecting the latch circuit LT and its gate is always supplied with a high voltage VPP. The transistor N
2
selects a fuse circuit in response to an address signal ADDi. The latch circuit LT holds data that is read out of the fuse element in read mode.
The second switch circuit
104
includes N-channel MOS transistors N
20
and N
21
, a NAND circuit ND
2
, and an inverter circuit IV
2
supplied with an output signal of the NAND circuit ND
2
. The input terminal of the NAND circuit ND
2
is supplied with a verify signal VRFY generated in verify mode and the bank select signal BSS. A connection node between the transistors N
20
and N
21
is connected to the other end portion of each of the fuse circuits
102
1
and
102
2
to
102
n
.
One end portion of the detection circuit
105
is connected to a pad
108
and the other end portion thereof is connected to the second switch circuit
104
through the second common wire
107
. The detection circuit
105
detects a current flowing through the fuse element FS in verify mode.
When a defective memory cell is found in a bank (not shown) in a manufacturing process of a semiconductor device, the fuse element FS is programmed in order to replace the defective memory cell with a spare memory cell.
When the fuse element FS is programmed, the program signal PRGM is activated to a high level. Then, the voltage generation circuit
101
generates a high voltage VBP.
In the first switch circuit
103
, the program signal PRGM and bank select signal BSS are set at a high level. The level of the output signal of the NAND circuit ND
1
is therefore low. The transistor N
11
that is supplied with the output signal through the inverter circuit IV
1
turns on, and the transistor N
10
that is supplied with the output signal turns off. Accordingly, the transistor P
10
turns on, while the transistor P
11
turns off.
In the second switch circuit
104
, the verify signal VRFY is set at a low level and the bank select signal BSS is set at a high level. The level of the output signal of the NAND circuit ND
2
is therefore high. The transistor N
20
that is supplied with the output signal via the inverter circuit IV
2
turns off, while the transistor N
21
that is supplied with the output signal turns on.
When the fuse circuit
102
1
is selected in response to the address signal ADDi in the state as described above, the high voltage VBP generated from the voltage generation circuit
101
is supplied through a path including the first common wire
106
, the transistor P
10
of the first switch circuit
103
, the fuse element FS, the transistors N
1
and N
2
, the transistor N
21
of the second switch circuit
104
, and the ground, as indicated by a broken line A. Thus, a high voltage is applied to the fuse element FS, and the fuse element is programmed to low resistance.
Then, the state of the programmed fuse element is verified. In the verify operation, the program signal PRGM is set to a low level and the verify signal VRFY is set to a high level. The bank select signal BSS is also set to a high level.
When the program signal PRGM is at a low level, the level of the output signal of the NAND circuit ND
1
of the first switch circuit
103
becomes high. The transistor N
10
that is supplied with the output signal turns on, while the transistor N
11
that is supplied with the output signal through the inverter circuit IV
1
turns off. Accordingly, the transistor P
11
turns on and the transistor P
10
turns off.
The level of the output signal of the NAND circuit ND
2
of the second switch circuit
104
becomes low in response to the verify signal VRFY and bank select signal BSS. Thus, the transistor N
21
that is supplied with the output signal turns off, while the transistor N
20
that is supplied with the output signal through the inverter circuit IV
2
turns on.
In this state, a voltage for verification, which is lower than the program voltage, is applied to the pad
108
. Thus, a current flows through a path including the detection circuit
105
, the transistor N
20
of the second switch circuit
104
, the transistors N
2
and N
1
, the fuse element FS, the transistor N
10
of the second switch circuit
103
, and the ground, as indicated by a thick broken line B. The detection circuit
105
detects a value of the current and accordingly the state of the fuse element FS is verified.
In order to program the fuse element FS with reliability, it is necessary to apply a high voltage of about 9V to the fuse element FS and pass a current of several milliamperes therethrough. To achieve this, the size of the transistors P
10
and N
21
composing the first and second switch circuits
103
and
104
, respectively, e.g., the channel width thereof is set larger than that of another transistor. Further, the size of the transistors N
1
and N
2
in each fuse circuit needs to increase.
In verify mode, a current flows through the transistor N
20
of the second switch circuit
104
and the transistor N
10
of the fi

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