Semiconductor device having dummy pattern

Details Semiconductor device having dummy pattern Semiconductor device having dummy pattern

2001-09-26

2003-09-02

Smith, Matthew S. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C257S207000, 43, C438S129000

Reexamination Certificate

active

06615399

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a method of arranging a dummy wire pattern that is prepared for processing needs, and the semiconductor device which has such dummy wire patterns.
2. Description of the Related Art
In recent years, the design ruling of semiconductor device has become finer and finer, causing difficulties in controlling a pattern width. As a parameter which controls the pattern width of wire patterns, a ratio of a resist pattern to a chip area (pattern density) is used. It has been known that a desired pattern can be formed with a satisfactory controllability by keeping the pattern density within a certain predetermined range.
When this pattern density is below the predetermined range, providing dummy wire patterns in addition to a wire pattern actually used (real wire pattern) has been practiced. By providing the dummy patterns, the pattern density is controlled to fall within the predetermined range.
Conventionally, the dummy pattern has been arranged by methods that follow.
The first method arranges dummy patterns to areas on a chip, where there is no wire present, at a certain distance from wires. By this method, the dummy pattern cannot be arranged efficiently.
The second method of solving this problem is to provide imaginary dummy patterns of a basic form (it is also called a unit dummy pattern or a virtual dummy pattern) in a lattice form at a certain interval. This method is described with reference to FIG.
1
.
FIG. 1
is a plan view showing a layout. In
FIG. 1
, there are two wires
1
and
2
that will be actually formed (real pattern) in addition to which unit dummy patterns
3
are laid at a predetermined interval (it is equal to or larger than the minimum interval standard, which is mentioned later). The squares in dashed line represent the group of the dummy patterns that are laid as described above. At this moment, each dummy pattern
3
is virtual. When processing in a CAD system, the dummy pattern group is treated as a virtual layer.
The dummy pattern group has a single coordinate system with its origin set at the center of the chip concerned on a wafer, for example.
The virtual dummy pattern is chosen as a real dummy pattern if distances in all directions to be measured (e.g., vertically and horizontally in
FIG. 1
) between each dummy pattern
3
of the virtual layer and the adjacent wires
1
and
2
are determined to be equal to or larger than the predetermined minimum interval standard serving as the wiring condition. The real dummy pattern will be actually formed on a chip with the wires
1
and
2
.
In arrangement of
FIG. 1
, when the unit dummy pattern
3
is located at the center between the wire
1
and wire
2
, the distance between a dummy pattern and each of the wires
1
and
2
should be equal to or larger than the minimum interval standard. To the contrary, the unit dummy pattern
3
in the center column is not positioned at the center between the wire
1
and the wire
2
, but is offset to the right as shown in FIG.
1
. Due to the offset, the distance D
1
of each dummy pattern
3
from the wire
2
is shorter than the minimum interval. In other words, each dummy pattern
3
in the center column is located in a position interfering with the wire
2
.
Therefore, each dummy pattern
3
in the center column is not chosen as a real pattern. Of course, the dummy patterns
3
of other two columns are not chosen, either. Consequently, there will be no dummy pattern formed at all between the wire
1
and the wire
2
. Therefore, the predetermined pattern density cannot be attained, causing a problem of uneven density.
The third conventional method is shown in FIG.
2
. The dummy pattern group used by the method shown in
FIG. 1
was arranged with the dummy patterns aligned in both column and row directions. Here, in the method shown in
FIG. 2
, dummy patterns are placed in a zigzag format. However, a dummy pattern group has a single coordinate system.
In
FIG. 2
, R
1
-R
7
indicate each line of dummy patterns. The lines R
1
, R
4
, and R
7
have the same dummy pattern arrangement (column positions of the dummy patterns are the same). The lines R
2
and R
5
have the same dummy pattern arrangement, having different column positions from other lines. The lines R
3
and R
6
have the same dummy pattern arrangement, having different column positions from other lines. That is, the same pattern is repeated every four lines.
In
FIG. 2
, two dummy patterns (occupying the line R
2
and R
5
, respectively, and on the same column position) indicated by the reference number
4
satisfy the minimum interval standard, and are chosen as the real dummy patterns. Therefore, the probability in which a real dummy pattern is inserted increases.
As described above, by the conventional method shown in
FIG. 2
, real dummy patterns can be laid out in a curtailed manner (dotted with dummy patterns), causing a problem that the pattern density is not effectively improving.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor device having a dummy pattern effectively laid out in addition to real patterns for wiring and the like for realizing the desired pattern density and a method thereof, which substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by the device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides the semiconductor device having dummy patterns such that the pattern density falls within the desired range, and a method thereof.
The present invention is to provide semiconductor device, which has real patterns such as wires and dummy patterns in different coordinate systems. Using a dummy pattern in a single coordinate system does not allow an effective dummy pattern arrangement. To the contrary, if the dummy patterns in different coordinate systems are used, minimum interval requirements may be satisfied in one coordinate system while such requirements are not met in another coordinate system. Therefore, dummy patterns functioning as a whole can be effectively arranged in addition to the real patterns such as wires.


REFERENCES:
patent: 5556805 (1996-09-01), Tanizawa et al.
patent: 6384464 (2002-05-01), Shin
patent: 2002/0061608 (2002-05-01), Kuroda et al.

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