Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2008-03-13
2010-12-28
Smith, Bradley K (Department: 2894)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C257SE21546
Reexamination Certificate
active
07858490
ABSTRACT:
A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.
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Chinese Office Action, w/ English translation thereof, issued in Patent Application No. CN 2005100914776 dated on Nov. 7, 2008.
Keeney, Stephen, N. “A 130nm Generation High Density Etox™ Flash Memory Technology.” 2001 International Electron Devices Meeting, p. 11 [online] URL: ftp://download.intel.com/research/silicon/.13micronflash—pres.pdf.
Mitsuhira Noriyuki
Nakahara Takehiko
Sumino Jun
Suzuki Yasusuke
Karimy Mohammad T
McDermott Will & Emery LLP
Renesas Electronics Corporation
Smith Bradley K
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