Semiconductor device having dual metal gates and method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

Reexamination Certificate

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C257S351000, C257S371000, C257S388000, C257S412000, C257SE27062

Reexamination Certificate

active

07838908

ABSTRACT:
A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2and alpha-silicon layers or a dBARC layer.

REFERENCES:
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patent: 6972224 (2005-12-01), Gilmer et al.
patent: 6974764 (2005-12-01), Brask et al.
patent: 7253050 (2007-08-01), Luan et al.
patent: 7432567 (2008-10-01), Doris et al.
patent: 2005/0106788 (2005-05-01), Amos et al.
patent: 2006/0289920 (2006-12-01), Wu et al.
patent: 2008/0188044 (2008-08-01), Hsu et al.
patent: 2008/0272433 (2008-11-01), Alshareef et al.
R. Ramachandran, et al.—“Method of Forming Gate Stack and Structure Thereof”—filed Jan. 5, 2009—U.S. Appl. No. 12/348,332.
M. Chudzik, et al.—High-K/Metal Gate Stack Using Capping Layer Methods, IC and Related Transistors—filed Dec. 12, 2007—U.S. Appl. No. 11/954,749.

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