Semiconductor device having delay-locked loop and test...

Details Semiconductor device having delay-locked loop and test... Semiconductor device having delay-locked loop and test...

2006-10-17

2006-10-17

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S201000, C327S149000, C327S158000

Reexamination Certificate

active

07123540

ABSTRACT:
A semiconductor device having a delay-locked loop includes: a variable delayer that delays a clock signal for a predetermined period of time to generate an internal clock signal; a normal pass that outputs data read from a memory cell outside the semiconductor device in response to the internal clock signal; a replica pass that has a substantial identical time delay to the normal pass and delays the internal clock signal to generate an output signal; and a phase detector that compares a phase of the clock signal with a phase of a predetermined feedback clock signal to control a time delay in the variable delayer. Here, the internal clock signal is output, instead of the output signal from the replica pass, as the predetermined feedback clock signal in a predetermined test mode.

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patent: 2002-324398 (2002-11-01), None
patent: 1020010047839 (2001-06-01), None
patent: P2003-0009030 (2003-01-01), None

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