Semiconductor device having delay circuit for receiving read...

Details Semiconductor device having delay circuit for receiving read... Semiconductor device having delay circuit for receiving read...

1998-03-13

2001-03-13

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S189050, C326S027000, C326S058000, C326S086000

Reexamination Certificate

active

06201743

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor device having an output buffer. Particularly, the present invention relates to a semiconductor device having an output buffer circuit which generates less noise due to the operation of the buffer circuit, and a semiconductor device which less affects the operation of any external circuitry due to the noise.
BACKGROUND TECHNOLOGY
There is a conventional output buffer circuit as shown in FIG.
2
.
The configuration of the conventional output buffer circuit is now explained hereinafter with reference to FIG.
2
.
The output buffer circuit comprises an output terminal OUT
1
on which output data appears, a p-channel MOS transistor (hereinafter referred to as PMOS)
129
and an n-channel MOS transistor (hereinafter referred to as NMOS)
130
.
An output transistor control circuit for controlling operations of these PMOS
129
and NMOS
130
is connected to gate electrodes of the PMOS
129
and NMOS
130
. The output transistor control circuit comprises inverters (hereinafter referred to as INVs)
120
,
122
,
125
,
133
, negative-conjunction circuits (hereinafter referred to as NAND circuits)
123
and
127
. The output transistor and the inverters and NAND circuits in the output transistor control circuit are connected to one another as follows.
A read instruction signal IN
1
is supplied to an input terminal of the INV
120
, and a node
121
is connected to an output terminal of the INV
120
. The node
121
is connected to an input terminal of the INV
122
, and a node
110
is connected to an output terminal of the INV
122
. An output signal node
131
, to which a signal corresponding to data to be outputted from the output terminal OUT
1
is inputted, is connected to an input terminal of the INV
133
and a node
132
is connected to an output terminal of the INV
133
. The node
110
and the node
132
are connected to an input terminal of the NAND circuit
123
, and a node
124
is connected to an output terminal of the NAND circuit
123
, respectively. The node
110
and the output signal node
131
are connected to an input terminal of the NAND circuit
127
, and a node
128
is connected to an output terminal of the NAND circuit
127
, respectively. The node
124
is connected to an input terminal of the INV
125
and a node
126
is connected to an output terminal of the INV
125
.
A source of the PMOS
129
is connected to a power supply VCC (a high voltage power supply is generally referred to as VCC) having a potential level of e.g. 3.3 V through a parasitic reactance L
2
of a power supply wire (a parasitic reactance generated along a path extending from a package terminal to an inside wiring chip). A gate of the PMOS
129
is connected to the node
128
and a drain thereof is connected to the output terminal OUT
1
. A source of the NMOS
130
is connected to a ground GND (a low voltage power supply is generally referred to as VSS or GND) having a potential level of e.g. 0 V through a parasitic reactance L
1
of a power supply (a parasitic reactance generated along a path ending from a package terminal to an inside wiring chip). A gate of the NMOS
130
is connected to the node
126
and a drain thereof is connected to the output terminal OUT
1
.
Connected to the input terminal of the INV
120
is a control circuit CONT
1
for outputting read instruction signal IN
1
corresponding to states of /RAS (Row Address Strobe Signal), /CAS (Column Address Strobe Signal), /OE (Output Enable Strobe Signal) and /WE (Write Enable Signal) respectively serving as multiple external input signals.
The control circuit outputs the read instruction signal IN
1
which changes from “L” level to “H” level in the states where the /WE (Write Enable Signal) is “H” level and the /RAS (Row Address Strobe Signal), /CAS (Column Address Strobe Signal) and /OE (Output Enable Strobe Signal) respectively change from “H” level to “L” level. A capacitor C
1
(normally 100 pF) is connected between the output terminal OUT
1
and the ground GND. The capacitor C
1
is provided outside the chip.
A resistor R
1
is connected between the output terminal OUT
1
and a reference voltage supply unit for supplying a reference voltage V
2
(normally 1.4 V). The output terminal OUT
1
and the reference voltage supply unit are also provided outside the chip.
The resistor R
1
, the capacitor C
1
and the reference voltage supply unit respectively provided outside the chip are needed for operating the output buffer circuit.
The operation of the output buffer circuit shown in
FIG. 2
will be now described with reference to FIG.
3
.
i) In case that “H” level is outputted from the output terminal OUT
1
(lower part in FIG.
3
).
In a period for not reading data, since the states of /RAS, /CAS, /OE and /WE serving as the external input signals hold “H” level, the control circuit CONT
1
outputs the read instruction signal IN
1
of “L” level.
In case that the read instruction signal IN
1
is “L” level, the node
128
goes to “H” level and the node
126
goes to “L” level so that both the PMOS
129
and NMOS
130
are turned off. Accordingly, the output terminal OUT
1
outputs “Hi-Z” level. Whereupon, the output terminal OUT
1
of the present circuit goes to “V
2
level” by the resistor R
1
and the reference voltage supply unit respectively provided outside the chip. Since this “V
2
level” is an intermediate level between “H” level and “L” level, it is recognized that “V
2
level” equals to “Hi-Z” level as viewed from an external device connected to the output terminal OUT
1
.
When the states of the /RAS, /CAS and /OE change from “H” level to “L” level while the /WE holds “H” level, the read instruction signal IN
1
changes from “L” level to “H” level. At this time, when the output signal node
131
is “H” level, the node
128
goes to “L” level and the node
126
goes to “L” level so that the PMOS
129
is turned on and the NMOS
130
is turned off. When the PMOS
129
is turned on, a current i
2
flows as shown in
FIG. 2
so that the potential level of the output terminal OUT
1
gradually increases. When the potential level of the output terminal OUT
1
reaches a given value (VOH, e.g., 2.0 V) or more, it is decided that the potential level of the output terminal OUT
1
is “H” level.
Thereafter, the read instruction signal IN
1
changes from “H” level to “L” level. When the read instruction signal IN
1
changes from “H” level to “L” level, the node
128
goes to “H” level so that the PMOS
129
is turned off. When the PMOS
129
is turned off, the potential level of the output terminal OUT
1
gradually decreases and finally goes to “Hi-Z” level. (Since the potential level of the output terminal OUT
1
returns to “Hi-Z” level, the operation thereof is hereinafter referred to as output reset).
ii) In case that “L” level is outputted from the output terminal OUT
1
(upper part in FIG.
3
).
On the other hand, since the node
128
goes to “H” level and the node
126
goes to “H” level when the output signal node
131
is “L” level in case that the read instruction signal IN
1
changes from “L” level to “H” level, the PMOS
129
is turned off and the NMOS
130
is turned on. When the NMOS
130
is turned on, a current i
1
flows as shown in
FIG. 2
so that the potential level of the output terminal OUT
1
gradually decreases. When the potential level of the output terminal OUT
1
reaches a given value (VOL, i.e., 0.8 V) or less, it is decided that the potential level of the output terminal OUT
1
is “L” level.
Thereafter, the read instruction signal IN
1
changes from “H” level to “L” level. When the output terminal OUT
1
changes from “H” level to “L” level, the node
126
goes to “L” level so that the NMOS
130
is turned off. When the NMOS
130
is turned off, the potential level of the output terminal OUT
1
gradually increases, and finally goes to “Hi-Z” level. (Since the potential level of the output terminal OUT
1
returns to “Hi-Z” level, the operation thereof is hereinafter referred to as output reset).
However, there was a case in the conventi

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