Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2007-07-03
2007-07-03
Smoot, Stephen W. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S678000, C438S682000, C438S685000, C438S686000, C438S740000, C257SE21165
Reexamination Certificate
active
10939148
ABSTRACT:
A conductive spacer (36, 122) in a sidewall region (30, 16) of a device (10, 100) is formed. The conductive spacer is formed adjacent sidewalls of the current electrode regions (18, 12). In one embodiment, a thin silicide layer (34) is formed at a top surface and a sidewall of the current electrode regions followed by an anisotropic etch of the conductive layer (32) used to form the thin silicide layer. The anisotropic etch of the conductive layer results in conductive spacers (36) adjacent sidewalls of the current electrode regions where these conductive spacers may allow for reduced contact resistance thus improving device performance. The conductive spacers may be formed adjacent current electrode regions of a MOSFET device, FINFET device, bipolar device, or Shotky-Barrier device.
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U.S. Appl. No. 10/695,163, filed Oct. 28, 2003.
Mathew Leo
Mathew Varughese
Chiu Joanna G.
Freescale Semiconductor Inc.
Hill Susan C.
Smoot Stephen W.
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