Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-08-29
2003-11-11
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S623000, C438S725000, C148SDIG007
Reexamination Certificate
active
06645850
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for creating cavities that are structured in submicrometer dimensions in a cavity layer of a semiconductor device by incorporating a swelling agent in a swellable processing material. The invention further relates to a configuration produced by the method, with cavities that are structured in submicrometer dimensions in a semiconductor device.
Inside a semiconductor device, conductive tracks are capacitively coupled to one another both within an interconnect layer (intralevel) and between different interconnect layers (interlevel). Such capacitive coupling between conductive tracks leads to crosstalk and prolonged signal transit times.
In order to minimize these disruptive effects, the conductive tracks are decoupled from one another as much as possible by minimizing the capacitance between them. Given a defined spacing between two conductive tracks, this requires an optimally low permittivity of the material between the conductive tracks. Gaseous substances such as air have an almost optimal permittivity of near 1 at normal pressure, whereas the permittivity of solid bodies is usually substantially higher.
For this reason, in semiconductor devices it is generally desirable to decouple two tracks from one another by air-filled cavities. The known methods for creating such air gaps will be described below. All the methods presume a working layer that has already been structured by ridges and trenches.
Conductive tracks can functionally emerge from the ridges of the working layer. The trenches of the working layer are cavities that are not yet covered. Accordingly, an interconnect layer is one possible embodiment of a cavity layer that emerges from a working layer, but not the only one.
According to a first method, the trenches are filled with porous materials such as xerogels or aerogels and then covered with a dielectric cover layer. The air that is trapped in the pores lowers the overall permittivity of the material between the tracks. Such porous materials are in the evaluation phase at present. The disadvantages of these methods are the water absorption owing to the capillary effect of the open-pored structures, and the relatively long processing times.
Furthermore, filling the cavities with xerogels and aerogels raises the permittivity of the cavity relative to a pure air fill. The utilization of aerogels as dielectric materials with low permittivity is described in the reference titled “The Effect of Sol Viscosity on the Sol-Gel Derived Low-Density SiO.sub.2 Xerogel Film For Intermetal Dielectric Application” (
Thin Solid Films,
vol. 332, pp. 449-454, 1998).
A second method is to cover trenches by conventional SiO
2
-CVD-processes (CVD=chemical vapor deposition) with a high deposition rate.
A first variant of such a method is described in the reference titled “Air-Gap Formation During IMD Deposition to Lower Interconnect Capacitance” (B. P. Shieh, IEEE Electron Device Letters, vol. 19, no. 1, pp. 16-18, January 1998). However, gaps that are generated in this fashion extend into the SiO
2
cover layer (cap formation). In subsequent CMP processes, the underlying cavities can be opened, and neighboring conductive tracks can be shorted by a subsequent metallization in the open cavities. If the SiO
2
layer is deposited with sufficient thickness to prevent a subsequent opening of the cavities, then the problem of contacting underlying tracks by way of sufficiently deep vias arises.
In a variant of the method that is described in the reference titled “Novel Air Gap Integration Scheme for Multi-Level Interconnects Using Self-Aligned Via Plugs” (T. Ueda, Symp. on VLSI Technology, pp. 46, 47, June 1998), the covering of the trenches is a two-stage process. In a first stage, SiO
2
is deposited on the horizontal surfaces of the ridges with a plasma enhanced chemical vapor deposition (PECVD) method. Narrow trenches are thus covered by SiO
2
that grows on both sides of the trenches on the surfaces of the ridges. In a high-density plasma CVD process, wider trenches are then filled with SiO
2
and narrow trenches are sealed with SiO
2
.
According to a third method as described in the reference titled “Use of Air-Gap Structures to Lower Intralevel Capacitance” (J. G. Fleming, E. Roherty-Osmum, Proc. DUMIC, pp. 139-45, 1997), spin-on materials are employed for covering the cavities between the tracks. The disadvantage of the method is the backflow of the materials into the cavities.
A fourth method is described in International Patent Disclosure WO 97/39484 A1 (Rosenmayer, Noddin). A film is laid on the interconnect layer that is structured by trenches and ridges. Such a film has a thickness of at least several micrometers, so that it can be safely processed. This gives rise to large spacings between the interconnect planes as described above, with the described disadvantages in connection with through-contacting by use of vias.
A fifth method, described in U.S. Pat. No. 6,165,890 (Kohl), is the retropolymerization of polynorbornene, which temporarily fills the cavities between the interconnects. In the method, unavoidable residues of the retropolymerization can lead to clusters that pose a short-circuiting risk. Furthermore, the selection of the dielectric material between interconnect layers is limited, because the material must be permeable to the volatile substances that emerge in the retropolymerization.
Similar disadvantages arise in a sixth method, the thermal decomposition of a temporary filling of the cavities between the conductive tracks. An example of a thermal decomposition of a temporary filling with a photoresist is described in U.S. Pat. No. 5,668,398 (Havemann). The oxidation of a temporary carbon layer is described in the reference titled “NURA: A Feasible Gas Dielectric Interconnect Process” (M. B. Anand, M. Yamada, H. Shibata, Symp. on VLSI Technology, pp. 82, 83, June 1996). In both cases, the substances that emerge in the decomposition must be expelled through the cover layer, which limits the material selection. The undecomposable residues in the cavities raise the permittivity, thereby reducing the resistance to shorting. According to another known example of the decomposition of a temporary filling, which is described in International Patent Disclosure WO 00/51177 (Werner, Pellerin), the cover layer is perforated prior to the decomposition of the filling in order to accelerate and thus improve the expulsion of the decomposition residues.
According to a seventh method, described in U.S. Pat. No. 5,599,745 (Reinberg), a dielectric layer is deposited on the ridges that are formed by the conductive tracks, this is melted enough that the layer arches over the track, and arches of the cover layer of closely adjacent tracks ultimately touch, bridging the trenches between them.
An eighth method for generating air gaps is described in U.S. Pat. No. 6,251,798 (Soo et al.). Here, in a first step a plasma-polymerized methyl silane is deposited on a structure having metal ridges such that it also fills the intermediate spaces between the metal ridges. The layer of plasma-polymerized methyl silane over the metal ridges is cured in sections by exposure. The plasma-polymerized methyl silane over the intermediate spaces between the metal ridges is partly covered during exposure, so that channels containing uncured plasma-polymerized methyl silane are formed from the surface to the spaces between the metallized ridges, which spaces are filled with uncured plasma-polymerized methyl silane. In a subsequent etching step, the uncured plasma-polymerized methyl silane is selectively etched against the cured plasma-polymerized methyl silane. It is thus removed also from the spaces between the metallized ridges by way of the channels.
The disadvantage of the method is that the curing must be adapted to the thickness of the deposited plasma-polymerized methyl silane layer. Furthermore, the plasma-polymerized methyl silane layer must be provided with a thickness of at least some 500 nanome
Leuschner Rainer
Mergenthaler Egon
Fourson George
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Pham Thanh
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