Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-04
2001-11-13
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S311000, C257S758000, C257S774000
Reexamination Certificate
active
06316801
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having capacitive elements and semiconductor devices having metal interconnection and ferroelectric capacitance or high dielectric capacitance.
In recent years, developments of ferroelectric memories utilizing ferroelectric capacitances and dynamic random access memories utilizing high dielectric capacitances have been active. Those ferroelectric memories and dynamic random access memories have switching transistors such as MOS field effect transistors. The ferroelectric capacitor or the high dielectric capacitor is electrically connected to one of diffusion regions, for example, source/drain diffusion regions so that the ferroelectric capacitor or the high dielectric capacitor can act as a memory cell in the ferroelectric memory or the dynamic random access memory.
The ferroelectric capacitor has a capacitive dielectric film made of a ferroelectric material, for example, Pb(Zr, Ti)O
3
, hereinafter referred to as “PZT”. Upon application of an electric field to the ferroelectric capacitive film the ferroelectric capacitive film shows a polarization which enables the ferroelectric capacitor to act the non-volatile storage
The high dielectric capacitor has a capacitive dielectric film made of a high dielectric material, for example, (Ba, Sr)TiO
3
, hereinafter referred to as “BST”. A high dielectric constant of the high dielectric film increases a capacitance of the high dielectric capacitor. This increase in capacitance of Ie high dielectric capacitor enables the capacitor to be scaled down.
For use of the ferroelectric capacitor or the high dielectric capacitor, it is necessary that one of electrodes of the ferroelectric capacitor or the high dielectric capacitor be connected to one of source/drain diffusion regions of switching transistor, for example, MOS field effect transistor.
In the dynamic random access memory, a bottom electrode of the capacitor may be made of a polysilicon, wherein the bottom electrode is connected to one of the source/drain diffusion regions of the switching transistors. The dielectric film is then formed on the polysilicon bottom electrode. The ferroelectric capacitive film and the high dielectric capacitive film are made of oxides, for example, Pb(Zr, Ti)
0
3
, and (Ba, Sr)TiO
3
, respectively. For this reason, if the ferroelectric capacitive film or the high dielectric capacitive film is formed on the polysilicon bottom electrode, then a top surface of the polysilicon bottom electrode may be oxidized by the ferroelectric capacitive film or the high dielectric capacitive film. The oxidation of the bottom electrode is of course problem. In order to have attempt to solve the above problem with oxidation of the surface of the polysilicon bottom electrode with the ferroelectric capacitive film or the high dielectric capacitive film, the following conventional methods had been proposed.
The first conventional method is disclosed in 1995 Symposium On VLSI Technology Digest Of Technical Papers, pp. 123, which describes a cell structure wherein a top electrode of the capacitor is connected to the describes that an oxide dielectric film of SrTiO
3
is formed on an RuO
2
/TiN bottom electrode formed on a polysilicon plug.
In accordance with the conventional methods of forming the ferroelectric memory and the dynamic random access memory, the capacitor has been formed, before a metal interconnection is then formed.
The above memory cell structure using the local interconnection or polysilicon plug connecting the capacitor to the diffusion region of the switching transistor has the following five problems.
The fist problem is in the difficulty to form multilevel metal interconnections. It is necessary to form multilevel metal interconnections in order to realize a high density integration of the ferroelectric memories having the ferroelectric thin films or the dynamic random access memories having the high dielectric thin films, or to realize a composite semiconductor device having such memory device and logic circuits. For forming the multilevel interconnections, an inter-layer insulator between adjacent different level interconnections is planarized by a chemical mechanical polishing method. However, the existence of the capacitor makes a difference in level of the inter-layer insulator between a memory cell array area having the capacitors and a logic circuit area free of any capacitor. This difference in level of the inter-layer insulator makes it difficult to planarize the surface of the inter-layer insulator. Otherwise, the difference in level of the inter-layer insulator makes it difficult to connect the adjacent different level interconnections to each other through a via hole or connect the first level interconnection to the diffusion region of the transistor through a contact hole but after the planarization to the inter-layer insulator. In Japanese laid-open patent publication No. 9-92794, it is disclosed that a difference in level of the inter-layer insulator between a memory cell area and a peripheral circuit area is reduced to form multilevel interconnections with reduced resistances on the peripheral circuit area. In accordance with this conventional method, after the via hole or the, contact hole has beer formed in the inter-layer insulator, then an electrically conductive material is deposited to fill the via hole or the contact hole and also to overly the inter-layer insulator, before the deposited conductive material is selectively etched to leave the same only within the via hole or the contact hole whereby the surface of the inter-layer insulator is shown. It is, however, difficult to realize a highly accurate etching to the electrically conductive material so that the electrically conductive material remains only the contact hole or the via hole without any over-etching to the surface of the inter-layer insulator.
The second problem is in an increase in the design cost for realizing the hybrid semiconductor integrated circuits having the logic circuits and the a semiconductor memories In order to settle the above first problem, it is required to change the process and device of the logic circuits. This means that the design parameters already used are no longer usable to other process.
The third problem is in deterioration in electrical characteristics of the capacitor or due to the process for forming the multilevel metal interconnections. Normally, a tungsten plug is formed in a via hole for connecting the adjacent different level metal interconnections. The tungsten film may be formed by utilizing, the following chemical reaction.
2WF
6
+3SiH
4
→2W+3SiH
4
+6F
4
.
The formation of the tungsten film is carried out in an extremely strong reduction atmosphere. Since the ferroelectric thin film and the high dielectric thin film are made, of oxides, exposure of the ferroelectric, thin film and the high dielectric thin film to the reduction atmosphere causes an oxygen deficiency of the ferroelectric thin film or the high dielectric thin film as the capacitive thin film whereby a resistance of the capacitive thin film is dropped whilst a leakage of current across the capacitive thin film increases. The oxygen deficiency further causes reductions in polarization of the ferroelectric film and in dielectric constant of the high dielectric film. The oxygen deficiency deteriorates the electrical characteristic of the capacitor.
In Japanese laid-open patent publication No. 9-199679, it was proposed to a, avoid the use of the reducing atmosphere for burying a metal into a deep contact hole. Plug contacts made of a thermally stable metal have been formed within openings which reach diffusion regions of CMOS circuits and memory circuits, before a ferroelectric capacitor is formed which is connected through some of the plug contacts to the diffusion regions, and further aluminum interconnections are formed in contact with the remaining ones of the plug contacts. The formation of this structure needs complicated processes. This conventional structural
Eckert II George C.
Lee Eddie
NEC Corporation
Young & Thompson
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