Active solid-state devices (e.g. – transistors – solid-state diode – With specified dopant
Reexamination Certificate
1998-02-17
2001-03-06
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With specified dopant
C257S610000, C257S611000, C257S913000, C257S914000
Reexamination Certificate
active
06198157
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention concerns a semiconductor wafer, a method of manufacturing the semiconductor wafer, a semiconductor device and a method of manufacturing the semiconductor device. More particularly, it relates to a technique effective for a wafer prepared by forming an epitaxial layer on the surface of a semiconductor substrate, namely, an epitaxial wafer and a semiconductor device using the same.
An epitaxial wafer is a semiconductor wafer of a structure in which an epitaxial layer, formed by epitaxial growth, is disposed on a main surface of a semiconductor wafer which has been mirror polished.
The epitaxial wafer is characterized by being excellent in reduction of soft errors and in latch-up protection, and the withstand voltage characteristic of a gate oxide film formed on the epitaxial layer is satisfactory, thereby remarkably reducing the defect density of the gate oxide film. It has been applied to the production technique for semiconductor integrated circuit devices. The method of manufacturing the epitaxial wafer is described, for example, in Japanese Patent Laid-Open Publication No. 7-45526 (Date of publication: Feb. 14, 1995, Applicant: Hitachi Ltd.).
In a silicon wafer substrate having such an epitaxial growth layer, the boron concentration (so-called substrate impurity concentration) is sometimes set to be higher than the concentration of the epitaxial growth layer in order to reduce latch-up and soft errors and provide gettering sites for heavy metal impurities, particularly for iron. Boron is introduced by a method of introduction during crystal growth and a method of introduction after crystal growth, for example, by ion implantation. For the latter, there has been known a method of manufacturing an epitaxial wafer by implanting boron ions into a silicon substrate and then applying epitaxial growth as disclosed, for example, in Japanese Patent Laid-Open Publication No. 8-17841 (Date of Publication: Jan. 19, 1996). Descriptions will be made hereinafter to the latter prior art.
The object of the prior art concerning an epitaxial substrate is to inhibit diffusion of oxygen from a substrate to an epitaxial layer and obtain an excellent gettering effect.
In the structure of the prior art, impurities to be implanted are ion implanted into a silicon substrate, and then heat treatment for forming nuclei for oxygen precipitation is applied, thereby forming a surface layer extending from the surface of the silicon substrate with a low concentration of the implanted impurities and a low density of nuclei for precipitation, a high density region formed therebelow with a high concentration of implanted impurities and a high density of nuclei for precipitation, and a low density region formed therebelow with a lower concentration of implanted impurities than that of the high density layer and with a lower density of nuclei for precipitation than that of the high density layer, and then an epitaxial layer deposited on the surface layer.
Then, in the prior art, it is disclosed that implanted impurities can be carbon or an impurity having a conductivity type identical with that of a silicon substrate (refer to page 4, right column, “0031”). That is, impurities to be implanted are selected to be either carbon or impurities of a conductivity type identical with that of the silicon substrate.
According to the invention disclosed in the prior art, a high concentration p-type silicon substrate having resistivity of 0.01 &OHgr;•cm or lower or an n-type silicon substrate having specific resistivity of 0.1 &OHgr;•cm or lower is applied as the silicon substrate (refer to page 5, right column, “0043”). That is, this prior art concerns an invention on the premise of a low resistivity substrate in which a great amount of impurities (0.01 &OHgr;•cm≈10
18
cm
−3
) are introduced, and carbon or impurities of a conductivity type identical with that of the silicon substrate is implanted into the substrate for promoting oxygen precipitation. Particularly, defects in the epitaxial layer caused by oxygen are reduced by lowering the concentration of implanted impurities at the surface layer of the substrate.
However, according to the prior art described above, since the semiconductor substrate has low resistance, there is a problem that the specific resistivity on the surface of the epitaxial layer fluctuates by diffusion from the bottom (rear face) of the substrate. In order to solve the problem, it may be considered to apply a coating of an oxide film to the bottom of the substrate. However, since such a treatment increases the number of manufacturing steps for the epitaxial wafer, it increases the cost of wafers.
In addition, during the heat treatment in the manufacturing step for a semiconductor device using such an epitaxial wafer, dislocations occur from the high boron concentration region in the semiconductor wafer (substrate) formed by ion implantation of boron. During the heat treatment in the manufacturing step of the semiconductor devices, these dislocations rise as far as a region forming the active region (surface of the epitaxial layer) of the semiconductor device to result in worsening of the yield of the semiconductor devices. This problem becomes more conspicuous as the thickness of the epitaxial layer is reduced in order to decrease the wafer cost.
It has been reported to conduct ion implantation of boron (B) and ion implantation of carbon (C) at a high energy into an Si crystal substrate obtained by a FZ method (Float Zone Growth Method) (so-called FZ-SI substrate) by Liefting et al (1992 Material Research Society Symp. Proc. Vol. 235, pp. 179-184; C IMPLANTATION FOR SUPPRESSION OF DISLOCATION).
However, Liefting et al. report the suppression of formation of defects to the FZ-SI substrate used for the manufacture of discrete devices such as diodes, transistors and thyristors. It was not disclosed for an Si crystal substrate obtained by the CZ method (Czochralski grown method) used for the manufacture of semiconductor integrated circuit devices (so-called CZ-Si substrate) and formation of an epitaxial layer on the surface of the CZ-Si substrate.
By the way, Kawagoe et al. propose a technique of providing an epitaxial wafer in which an epitaxial layer is formed to a thickness of not more than 5 &mgr;m (specifically, 1 &mgr;m) on the surface of a CZ-Si substrate having a high specific resistivity, and forming an MOS•FET on the surface of the epitaxial wafer as disclosed in Japanese Patent Laid-Open Publication No. 8-97163 (Date of Publication; Apr. 12, 1996). Particularly, they propose to deposit polysilicon (polycrystalline silicon) as a gettering layer on the rear face of the wafer in order to improve gettering of heavy metal impurities in the epitaxial wafer.
However, according to the study made by the inventors of the present application, it has been found that the heavy metal impurities can not be gettered sufficiently with the gettering layer formed thus on the rear face of the wafer.
Further, formation of the gettering layer increases the cost of the epitaxial wafer.
In view of the above, the present inventors have attempted to form a gettering layer at high concentration by ion implantation into the substrate of impurities having a conductivity type identical with that of the substrate (specifically, boron), as another means for improving the gettering performance of the epitaxial wafer using the CZ-Si substrate having a high specific resistivity. However, such means induces dislocations to occur from the high boron impurity concentration region in the semiconductor wafer (substrate) formed by ion implantation of boron during a heat treatment in the manufacturing steps for the semiconductor devices, like in the case of the prior art as described above. During the heat treatment in the manufacturing steps for the semiconductor devices, dislocations rise as far as the surface of the epitaxial layer, resulting in worsening the yield of the semiconductor devices.
Accordingly, the present inventors have made a further
Ishida Hidetsugu
Isomae Seiichi
Antonelli Terry Stout & Kraus LLP
Baumeister Bradley W.
Hitachi , Ltd.
Saadat Mahshid
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