Semiconductor device having bipolar transistor and MOS...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S378000

Reexamination Certificate

active

06337501

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application is based upon Japanese Patent Application Nos. Hei. 11-101702 filed on Apr. 8, 1999, and Hei. 11-359768 filed on Dec. 17, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices, and particular to a semiconductor device including a bipolar transistor and a insulated gate transistor, and a circuit using the semiconductor device.
2. Related Art
Conventionally, several semiconductor devices in which each element region is separated by being insulated each other by using a PN junction or an insulating film, and in which semiconductor element such as a bipolar transistor or an insulated gate transistor is formed in each of the element regions, have been proposed (JP A 6-267966, JP A 6-268054, etc).
According to the above-described semiconductor devices, the bipolar transistor and the insulated gate transistor are individually formed in separated element regions. Therefore, when the bipolar transistor is electrically connected to the insulated gate transistor, it needs to provide a metallic wire such as aluminum wire. In this case, a circuit layout pattern may become large.
SUMMARY OF THE INVENTION
This invention has been conceived in view of the background thus far described and its first object is to prevent a circuit layout pattern from being large due to a wiring.
Its second object is to provide one of a circuit device, a comparator, and an oscillator, which uses a semiconductor device capable of preventing a circuit layout pattern from being large due to a wiring.
According to the present invention, an element region is formed in the substrate by being isolated and insulated from the other element regions to be formed in the substrate. In a semiconductor layer formed in the element region, a bipolar transistor, which is made up of: a base region having a second conductivity type; an emitter region having the first conductivity type; and a collector region having the first conductivity type, is formed. In this semiconductor layer in which the bipolar transistor is formed, an insulated gate transistor is formed by using the base region as one of a source and a drain thereof.
Since the bipolar transistor and the insulated gate transistor are commonly formed in an element region, and one of regions is commonly used, it can prevent a circuit layout pattern from being large due to a wiring for connecting the bipolar transistor and the MOS transistor.


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patent: 4244001 (1981-01-01), Ipri
patent: 4400711 (1983-08-01), Avery
patent: 4893158 (1990-01-01), Mihara et al.
patent: 4954865 (1990-09-01), Rokos
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patent: 5449946 (1995-09-01), Sakakibara et al.
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patent: 5679972 (1997-10-01), Kim
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patent: 5932916 (1999-08-01), Jung
patent: 49-74488 (1972-11-01), None
patent: 53-60582 (1978-05-01), None
patent: 2-4013 (1990-01-01), None

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