Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-01-21
2001-04-10
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S573000, C257S576000, C257S584000, C257S587000, C257S588000, C438S677000, C438S974000
Reexamination Certificate
active
06215160
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and a method of manufacturing the same, and more particularly to a semiconductor device having a Bi-CMOS element and a method of manufacturing the same.
2. Description of the Background Art
Conventionally, a Bi-CMOS element is known as one which combines high speed characteristics of a bipolar element and high integration characteristics and low power consumption characteristics of a CMOS element.
FIG. 33
is a cross sectional view showing a semiconductor device having a conventional Bi-CMOS element. Referring to
FIG. 33
, in the semiconductor device having the conventional Bi-CMOS element, an N-channel MOS transistor, a P-channel MOS transistor, and an NPN bipolar transistor are formed adjacent to each other on a P
−
type semiconductor substrate
101
. Element isolation regions are provided between the N-channel MOS transistor and the P-channel MOS transistor, and between the P-channel MOS transistor and the NPN bipolar transistor, respectively.
In the N-channel transistor region, a P
+
type buried layer
103
is formed on P
−
type semiconductor substrate
101
. A P-type well
107
is formed on P
+
type buried layer
103
. On a main surface of P type well
107
, N
+
type source/drain regions
115
a
and
115
b
are formed with a prescribed space so as to sandwich a channel region. On the channel region sides of N
+
type source/drain regions
115
a
and
115
b
, N
−
type source/drain regions
112
a
and
112
b
are formed, respectively. On the channel region a lower polycrystalline silicon film
118
c
is formed with a gate oxide film
117
c
interposed therebetween. An upper polycrystalline silicon film
119
c
is formed on lower polycrystalline silicon
118
c
. Lower polycrystalline silicon film
118
c
and upper polycrystalline silicon film
119
c
constitute a gate electrode. Sidewall oxide films
120
c
are formed on both side surfaces of lower polycrystalline silicon film
118
c
and upper polycrystalline silicon film
119
c.
In the P-channel MOS transistor region, an N
+
type buried layer
102
is formed on P
−
type semiconductor substrate
101
. An N-well
106
is formed on N
+
buried layer
102
. On a main surface of an N-well
106
P
+
type source/drain regions
114
a
and
114
b
are formed with a prescribed space so as to sandwich a channel region. P
−
type source/drain regions
111
a
and
111
b
are formed respectively on the channel region sides of P
+
type source/drain regions
114
a
and
114
b
. On the channel region a lower polycrystalline silicon film
118
b
formed with a gate oxide film
117
b
interposed therebetween. An upper polycrystalline silicon film
119
b
is formed on lower polycrystalline silicon film
118
b
. Lower polycrystalline silicon film
118
b
and upper polycrystalline silicon film
119
b
constitute a gate electrode. Sidewall oxide films
120
b
are formed on both side surfaces of lower polycrystalline silicon film
118
b
and upper polycrystalline silicon film
119
b.
In the NPN bipolar transistor region, N
+
type buried layer
102
is formed on P
−
type semiconductor substrate
101
. An N
−
type epitaxial layer
104
is formed on N
+
type buried layer
102
. In a prescribed region of N
−
type epitaxial layer
102
, an N
+
type collector electrode drawing-out layer
108
is formed extending from its surface down to N
+
type buried layer
102
. On a main surface of N
−
type epitaxial layer
104
, a P-type base layer
109
and a P
+
external base layer
113
are formed with a prescribed space from N
+
type collector electrode drawing-out layer
108
. An N
+
type emitter layer
110
is formed in a prescribed region on a main surface of P type base layer
109
. A gate oxide film
117
a
having an opening on N
+
type emitter layer
110
is formed in a prescribed region on P type base layer
109
. A lower polycrystalline silicon film
118
a
is formed on gate oxide film
117
a
. An upper polycrystalline silicon film
119
a
is formed electrically connected to N
+
type emitter layer
110
, and extending on and along an upper surface of lower polycrystalline silicon film
118
a
. Lower polycrystalline silicon film
118
a
and upper polycrystalline silicon film
119
a
constitute an emitter electrode. A sidewall oxide film
120
a
is formed on a sidewall portion of lower polycrystalline silicon film
118
a
and upper polycrystalline silicon film
119
a
. An isolation oxide film
116
is formed between N
+
type collector electrode drawing-out layer
108
and P
+
type external base layer
113
.
In the element isolation region between the transistors, isolation oxide film
116
, a P
+
type element isolation layer
105
, and P
+
type buried layer
103
are formed. A surface protection oxide film
121
is formed to cover the whole surface. A contact hole is formed in a region corresponding to an electrode formation region of surface protection oxide film
121
. A collector electrode wiring
122
, a base electrode wiring
123
, an emitter electrode wiring
124
, a source/drain electrode wiring
125
of the P-channel MOS transistor, a gate electrode wiring, not shown, of the P-channel MOS transistor, a source/drain electrode wiring
126
of the N-channel MOS transistor, and a gate electrode wiring, not shown, of the N-channel MOS transistor are respectively formed to bury the corresponding contact holes.
Gate oxide films
117
a
,
117
b
and
117
c
are formed to have a thickness of approximately 10 nm, respectively. Lower polycrystalline silicon films
118
a
,
118
b
, and
118
c
are formed to have a thickness of approximately 20-70 nm, respectively. Upper polycrystalline silicon films
119
a
,
119
b
and
119
c
are formed to have a thickness of approximately 150-200 nm , respectively. Surface protection oxide film
121
is formed to have a thickness of approximately 1000 nm.
FIGS. 34
to
39
are sectional views showing a method of manufacturing the semiconductor device including the conventional Bi-CMOS element shown in FIG.
33
. The method of manufacturing the semiconductor device including the conventional Bi-CMOS element will now be described with reference to
FIGS. 34
to
39
.
Initially, as shown in
FIG. 34
, after arsenic (As) or antimony (Sb) is ion-implanted into the bipolar transistor formation region and the P-channel MOS transistor formation region on P
−
type semiconductor substrate
101
, heat treatment is carried out, so that N
+
type buried layer
102
is formed. After boron (B) is ion-implanted into the N-channel MOS transistor formation region and the element isolation region, heat treatment is carried out, so that P
+
type buried layer
103
is formed. N
−
type epitaxial layer
104
is formed all over the surface. Isolation oxide films
116
are formed in the element isolation regions and the collector-base isolation region of the bipolar transistor, with a LOCOS (LOCal Oxidation of Silicon) method.
The collector electrode formation region of the bipolar transistor is subjected to solid phase diffusion with phosphorus (P) to form N
+
type collector electrode drawing-out layer
108
. After boron (B) is ion-implanted through isolation oxide film
116
in the element isolation region, heat treatment is carried out, so that P
+
type element isolation layer
105
is formed.
After phosphorus (P) is ion-implanted into the P-channel MOS transistor region, heat treatment is carried out, so that N-type well
106
is formed. After boron (B) is ion-implanted into the N-channel MOS transistor region, heat treatment is carried out, so that P-type well
107
is formed.
As shown in
FIG. 35
, after boron (B) is ion-implanted into N
−
type epitaxial layer
104
of the bipolar transistor region, heat treatment is carried out, so that P-type base layer
109
is formed.
As shown in
FIG. 36
, thermal ox
Abraham Fetsum
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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