Semiconductor device having automatic controlled delay...

Details Semiconductor device having automatic controlled delay... Semiconductor device having automatic controlled delay...

2006-02-21

2006-02-21

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S189070, C365S189090, C365S191000

Reexamination Certificate

active

07002857

ABSTRACT:
An automatic controlled delay circuit for use in a semiconductor memory device capable of detecting and adjusting a variation in delay with PVT variation delays a wordline activating signal by a predetermined time period and outputs the same as a bitline sense amplifier activating signal. The delay circuit is implemented with a plurality of delay blocks that are connected serially. The semiconductor device comprises a delay pulse signal generating block for generating a plurality of delayed pulse signals, each of which has different delay values at a time point at which the wordline activating signal is activated using an internal clock; a signal detecting block for detecting an activation time point of the bitline sense amplifier activating signal to generate a detected pulse signal; and a delay amount adjusting block for comparing the plurality of delayed pulse signals with the detected pulse signal to control the plurality of delay blocks.

REFERENCES:
patent: 6269051 (2001-07-01), Funaba et al.

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