Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Patent
1998-05-20
2000-08-01
Jackson, Jr., Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Fet configuration adapted for use as static memory cell
257377, 257775, H01L 2711
Patent
active
060971037
ABSTRACT:
P.sup.+ -type source/drain regions for load transistors and N.sup.+ -type source/drain regions for driver transistors are connected by means of P.sup.+ -type source/drain region outgoing lead and N.sup.+ -type source/drain region outgoing lead via direct contact holes. The drain region outgoing lead for the load transistors and ground lead are formed in a three-dimensionally overlapping manner, and the drain region outgoing lead for the driver transistors connected to memory nodes on one side and the drain region outgoing lead for the load transistors connected to memory nodes on the other side are also formed in a three-dimensionally overlapping manner, whereby memory node charge accumulators are constituted.
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patent: 5717240 (1998-02-01), Kuriyama et al.
patent: 5821590 (1998-10-01), Lee et al.
Eckert II George C.
Jackson, Jr. Jerome
Mitsubishi Denki & Kabushiki Kaisha
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