Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2001-01-04
2004-04-20
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S775000
Reexamination Certificate
active
06724092
ABSTRACT:
BACKGROUND OF INVENTION
1. Technical Field of the Invention
The present invention relates to a semiconductor device having a wiring pattern that is formed by etching a conductive layer using a resist pattern as a mask, and a method for manufacturing the same.
2. Background of the Invention
First, a general method for manufacturing wiring patterns in a semiconductor device is described.
FIG. 6
shows a plan view of a mask pattern for forming resist patterns.
FIG. 7
shows a plan view of wiring patterns that are formed by using resist patterns obtained by the mask pattern shown in FIG.
6
.
FIG. 8
shows a cross-sectional view taken along lines A—A of FIG.
7
.
FIG. 9
shows a cross-sectional view taken along lines B—B of FIG.
7
.
First to third line patterns
105
to
107
in the mask pattern shown in
FIG. 6
are patterns for forming wirings. The mask pattern of this kind is generally formed by using a commonly available CAD system. Resist patterns are formed by lithography using the mask pattern. A conductive layer is etched using the resist patterns as masks to form wiring layers. Then, the resist is removed by a known method. The wiring patterns obtained in this manner are shown in FIG.
7
.
In the example shown in
FIG. 7
, a second wiring
115
is disposed in parallel with a first wiring
117
. Further, a third wiring
116
is disposed in a direction perpendicular to the first wiring
117
. Furthermore, one end of the second wiring
115
is connected to a contact section
130
formed in an interlayer dielectric layer
120
. The contact section
130
is formed from a metal layer embedded in a via-hole
113
. Also, one end of the third wiring
116
is connected to a contact section
132
embedded in a via hole
114
. It is noted that, in
FIG. 7
, wirings in a layer lower than the wirings shown in the figure are not shown.
In the mask patterns that are used to form the first to third wirings having such patterns, as shown in
FIG. 6
, the second line pattern
105
is designed to extend to an extent to cover a via hole pattern
103
in such a manner that an end section of the second line pattern
105
generally concurs with an end section of the via hole pattern
103
. Similarly, the third line pattern
106
is designed to extend to an extent to cover a via hole pattern
104
in such a manner that an end section of the third line pattern
106
generally concurs with an end section of the via hole pattern
104
.
Incidentally, when wirings are formed by an etching method using resist patterns as masks, the following characteristic conditions take place. Namely, the wirings that are etched in a portion where the resist patterns are roughly formed become generally thicker than the resist patterns, and the wirings that are etched in a portion where the resist patterns are densely formed become generally thinner than the resist patterns. These conditions are shown in FIG.
8
and FIG.
9
.
FIG. 8
shows the condition that occurs when the patterns are rough. In this condition, when the etching is conducted, tapers are formed on the sides of the wiring
117
. As a result, the width of the wiring
117
becomes wider than the width of the resist.
FIG. 9
shows the condition where the wirings are not isolated. Under this condition, tapers are not formed on the opposing sides of the wiring
115
and the wiring
117
.
Also, when resists are receded with further miniaturization of wiring patterns, there are instances where an overlap region between the contact section
130
in the via hole
113
and the second wiring
115
and an overlap region between the contact section
132
in the via hole
114
and the third wiring
116
become insufficient. As a result, problems may occur. For example, the contact resistances between the wirings
115
and
116
and the contact sections
130
and
132
may increase, the wiring reliability lowers, and so fourth.
Also, as shown in
FIG. 7
, since wiring patterns are not present adjacent to a region between the via holes
113
and
114
disposed on one side of the first wiring
117
, a taper is formed on a side of the first wiring
117
as the etching is conducted, as shown in
FIG. 8
, and thus a bottom section of the wiring
117
becomes thicker than an upper section thereof. As a result, a protruded region
117
a
that is different from the resist pattern is formed in the first wiring
117
. Due to the protruded region
117
a
, separations L
1
and L
2
between the wiring
117
and the contact sections
130
and
132
become smaller than the specified minimum inter-wiring separations. As a result, defects may occur in that the contact sections and the wirings become short-circuited.
As described above, in the conventional common semiconductor device, overlap regions between connection holes (via holes or contact holes) and wirings become insufficient as resists are receded with further miniaturization of patterns. This results in problems, such as, for example, the contact resistance between the wiring and the contact section embedded in the connection hole increase, and the wiring reliability lowers. Also, in regions where wiring patterns are roughly formed, wirings become wider than the corresponding resists due to tapers formed during the etching step. As a result, the thicker wiring sections may become short-circuited with contact sections formed nearby in a lower layer.
SUMMARY OF THE INVENTION
In accordance with the present invention, a semiconductor device that has a wiring pattern that is formed by etching a conductive layer using a resist pattern as a mask includes
a contact section formed in an interlayer dielectric layer,
a first wiring formed over the interlayer dielectric layer and disposed with a separation from the contact section shorter than a specified separation, and
a second wiring having a connection region to be connected to the contact section,
wherein the second wiring has an extension section extending in a non-wiring region in the connection region to be connected to the contact section, and
the extension section is disposed in at least one section of the connection region other than sides thereof facing the first wiring.
In the semiconductor device in accordance with the present invention, since the extension section is provided in the connection region to be connected to the contact section, the connection region of the wiring can almost completely cover the contact section in the lower layer. Therefore, the contact resistance between the contact section formed in the connection hole (contact hole or via hole) and the wiring can be made small, the wiring reliability can be improved.
A variety of embodiments may be provided for the semiconductor device of the present invention as described below. These embodiments are applicable to semiconductor devices having structures to be described below.
(a) The separation is shorter than a specified separation and there is a minimum separation between wirings in a wiring pattern (hereafter referred to as a “minimum inter-wiring separation”). The minimum inter-wiring separation may vary depending on the design rules, and may be, for example, 0.1 &mgr;m or greater but 1 &mgr;m or smaller.
(b) The connection region is square in its plan configuration having dimensions that are greater than or equal to dimensions of the contact section.
(c) The extension section may preferably have the same width as the width of the wiring, and may preferably have the same extension length as the width of the wiring. Also, the extension section may preferably be square in its plan configuration.
Furthermore, semiconductor device in accordance with the present invention can have the following structures.
(1) A semiconductor device includes
a contact section formed in an interlayer dielectric layer,
a first wiring formed over the interlayer dielectric layer and disposed with a minimum inter-wiring separation with respect to the contact section, and
a second wiring having a connection region to be connected to the contact section and extending in parallel with the first wiring,
wherein the connection
Cao Phat X.
Hogan & Hartson LLP
Seiko Epson Corporation
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