Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2009-09-02
2011-11-22
Verbrugge, Kevin (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711SE12008
Reexamination Certificate
active
08065471
ABSTRACT:
A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second, third, and fourth memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the third memory area, a fourth processing for moving an area of the third unit having the oldest allocation order in the fourth memory area to the second memory area, and a fifth processing for selecting data in the second memory area and copying the selected data to an empty area of the third unit in the second memory area.
REFERENCES:
patent: 7496811 (2009-02-01), Kanno
patent: 7551478 (2009-06-01), Kanno
patent: 2006/0064538 (2006-03-01), Aizawa
patent: 2006/0179212 (2006-08-01), Kim et al.
patent: 2007/0028034 (2007-02-01), Nishihara
patent: 2007/0130496 (2007-06-01), Kanno
patent: 2008/0028132 (2008-01-01), Matsuura et al.
patent: 2008/0205145 (2008-08-01), Kanno et al.
patent: 2009/0183052 (2009-07-01), Kanno et al.
patent: 2010/0274950 (2010-10-01), Yano et al.
patent: 2010/0281204 (2010-11-01), Yano et al.
patent: 10-116230 (1998-05-01), None
patent: 2002-278828 (2002-09-01), None
patent: 2002-366423 (2002-12-01), None
patent: 2005-222550 (2005-08-01), None
U.S. Appl. No. 12/544,272, filed Sep. 4, 2009, Yoshii, et al.
U.S. Appl. No. 12/563,856, filed Sep. 21, 2009, Yano, et al.
Jo et al., “FAB: flash-aware buffer management policy for portable media players,” Consumer Electronics, IEEE Transactions on, May 2006, vol. 52, Issue 2, pp. 485-493.
Lee et al., “A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation,” ACM Transactions on Embedded Computing Systems, vol. 6, No. 3, Article 18, Jul. 2007.
U.S. Appl. No. 13/052,146, filed Mar. 21, 2011, Ootsuka, et al.
Asano Shigehiro
Hida Toshikatsu
Kanno Shin-ichi
Kitsunai Kazuya
Matsuzaki Hidenori
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Verbrugge Kevin
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