Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-30
2002-10-01
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S334000, C257S302000, C257S301000
Reexamination Certificate
active
06459122
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a U-grooved metal oxide semiconductor (UMOS)-structure, wherein a gate is provided in a groove of a body of the semiconductor device.
2. Description of the Related Art
The semiconductor device with the UMOS-structure has one or more parallel connections of plural unit cells which comprise MOS field effect transistors. The UMOS-structure has U-grooves formed in the body of the semiconductor device. The UMOS-structure also has channel layers formed in the U-grooves. In detail, the channel layers vertically extend on side walls of the U-grooves, so as to increase the degree of integration of the unit cells. Namely, the UMOS-structure allows a higher degree of integration of the unit cells than the gate-planer type semiconductor device, wherein channel layers horizontally extend on a surface of the body of the semiconductor device. The UMOS-structure allows the increase in channel width per a unit area. This reduces an ON-resistance of the device.
The U-groove is so designed that its depth is fixed but its width is adjusted in accordance with the required source-drain withstand voltage. The U-groove is formed by a selecting etching process using a mask pattern. The width of the groove is defined by the mask pattern width. For example, if the required source-drain withstand voltage is in the range of 20-60 V, then the mask pattern width may be 1 micrometer. If the required source-drain withstand voltage is in the range of 100-120 V, then the mask pattern width may be 4 micrometers. If the required source-drain withstand voltage is in the range of 200-250 V, then the mask pattern width may be 8 micrometers. The increase in the width of the groove increases the source-drain withstand voltage.
FIG. 1
is a fragmentary cross sectional elevation view of a conventional UMOS-structure of a semiconductor device, wherein a groove width is 1 micrometer. A semiconductor device
100
has a semiconductor body
1
which comprises an n+-type silicon substrate
2
and an epitaxial layer
4
overlying the n+-type silicon substrate
2
. The epitaxial layer
4
has a lattice-pattern in plan view of U-grooves
3
which have a U-shape in vertically cross sectional view. Each of the U-grooves
3
has a bottom width of 1 micrometer. Gate insulating films
5
extend on the side walls and the bottom of the U-grooves
3
and also over peripheral top surface regions of the epitaxial layer, wherein the peripheral top surface region is adjacent to and surrounds the U-groove
3
. Gate electrodes
6
are provided, which extend on the gate insulating films
5
so that a majority part of the gate electrode
6
is positioned within the U-groove
3
. The gate electrodes
6
comprise polysilicon films.
The epitaxial layer
4
includes an n−-type drain region
7
, a p-type base region
8
, p+-type back gate regions
9
, and n+-type source regions
10
, The n−-type drain region
7
overlies the n+-type silicon substrate
2
. The p-type base region
8
overlies the n−-type drain region
7
. The U-grooves
3
penetrate the p-type base region
8
and reach the upper portions of the n−-type drain region
7
. The p+-type back gate regions
9
are selectively provided in the p-type base region
8
, so that each of the p+-type back gate regions
9
is separated by the p-type base region
8
from the adjunct U-grooves
3
and also from the n−-type drain region
7
. The n+-type source regions
10
are selectively provided in upper regions of the p-type base region
8
and the p+-type back gate regions
9
. The n+-type source regions
10
are adjacent to the upper regions of the adjunct U-grooves
3
.
Inter-layer insulators
11
are selectively provided over the gate electrodes
6
and the gate insulating films
5
, so that the inter-layer insulators
11
cover the gate electrodes
6
and the gate insulating films
5
. The inter-layer insulators
11
do not overly parts of the n+-type source regions
10
and the p+-type back gate regions
9
. A source electrode
12
is provided which overlies the inter-layer insulators
11
, the n+-type source regions
10
and the p+-type back gate regions
9
, so that the source electrode
12
has an ohmic contact with the n+-type source regions
10
and the p+-type back gate regions
9
. Parts of the source electrode
12
over the unit cells also serve as source pads which allows external electrical connections.
FIG. 2
is a fragmentary cross sectional elevation view of another conventional UMOS-structure of a semiconductor device, wherein a groove width is 8 micrometers. A semiconductor device
200
has a semiconductor body
21
which comprises an n+-type silicon substrate
22
and an epitaxial layer
24
overlying the n+-type silicon substrate
22
. The epitaxial layer
24
has a lattice-pattern in plan view of U-grooves
23
which have a U-shape in vertically cross sectional view. Each of the U-grooves
23
has a bottom width of 8 micrometers. Gate insulating films
25
extend on the side walls and the bottom of the U-grooves
23
and also over peripheral top surface regions of the epitaxial layer, wherein the peripheral top surface region is adjacent to and surrounds the U-groove
23
. Gate electrodes
26
are provided, which extend on the gate insulating films
25
, so that a majority part of the gate electrode
26
is positioned within the U-groove
23
. The gate electrodes
26
comprise polysilicon films.
The epitaxial layer
24
includes an n−-type drain region
27
, a p-type base region
28
, p+-type back gate regions
29
, and n+-type source regions
30
. The n−-type drain region
27
overlies the n+-type silicon substrate
22
. The p-type base region
28
overlies the n−-type drain region
27
. The U-grooves
23
penetrate the p-type base region
28
and reach the upper portions of the n−-type drain region
27
. The p+-type back gate regions
29
are selectively provided in the p-type base region
28
, so that each of the p+-type back gate regions
29
is separated by the p-type base region
28
from the adjunct U-grooves
23
and also from the n−-type drain region
27
. The n+-type source regions
30
are selectively provided in upper regions of the p-type base region
28
and the p+-type back gate regions
29
. The n+-type source regions
30
are adjacent to the upper regions of the adjunct U-grooves
23
.
Inter-layer insulators
31
are selectively provided over the gate electrodes
26
and the gate insulating films
25
, so that the inter-layer insulators
31
cover the gate electrodes
26
and the gate insulating films
25
. The inter-layer insulators
31
do not overly parts of the n+-type source regions
30
and the p+-type back gate regions
29
. A source electrode
32
is provided which overlies the inter-layer insulators
31
, the n+-type source regions
30
and the p+-type back gate regions
29
, so that the source electrode
32
has an ohmic contact with the n+-type source regions
30
and the p+-type back gate regions
29
. Parts of the source electrode
32
over the unit cells also serve as source pads which allows external electrical connections.
The semiconductor device
100
shown in
FIG. 1
ensures the source-drain withstand voltage in the range of 20-60 V, for which purpose, the U-grooves
3
are designed so that the groove width is 1 micrometer, and that a diffusion depth of the p-type base region
8
is shallower than a depth of the U-grooves
3
. Further, since the U-grooves
3
are narrow, the source electrode
12
has a generally flat top surface.
The semiconductor device
200
shown in
FIG. 2
ensures the source-drain withstand voltage in the range of 200-250 V, for which purpose, the U-grooves
23
are designed so that the groove width is 8 micrometers, and that a diffusion d
Le Dung A
Nelms David
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