Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1996-09-06
2004-02-17
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S775000, C257S412000
Reexamination Certificate
active
06693324
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof and, more particularly, to a semiconductor device having a thin film transistor and a manufacturing method thereof.
2. Description of the Background Art
Conventionally, a thin film transistor with a so-called DELTA structure has been proposed as a thin film transistor. The thin film transistor with the DELTA structure is described, for example, by D. Hisamoto et al., in “Impact of the Vertical SOI ‘DELTA’ Structure on Planar Device Technology”
IEEE TRANSACTIONS ON ELECTRON DEVICES
, VOL. 38, No. 6, JUNE, 1991, pp. 1419-1424. Description will be made hereinafter of such thin film transistor with the DELTA structure as a conventional thin film transistor.
FIG. 48
is a perspective view schematically showing the structure of the conventional thin film transistor. Referring to
FIG. 48
, a monocrystalline silicon layer
203
is formed on a silicon substrate
220
with a field oxide film
221
interposed therebetween, thereby forming an SOI (Silicon On Insulator) structure. A pair of source/drain regions
203
a
and
203
b
are formed at monocrystalline silicon layer
203
so as to define a channel region. A gate electrode layer
207
is formed to face the channel region with a gate insulating film (not shown) interposed therebetween. Monocrystalline silicon layer
203
has a width W
2
of approximately 0.2 &mgr;m and a height H
2
of approximately 0.4 &mgr;m where width W
2
is set smaller than height H
2
.
Next, description will be made of a method of manufacturing the conventional thin film transistor (FIG.
48
).
FIGS. 49-52
are schematic cross-sectional views showing in order of the steps the method of manufacturing the conventional thin film transistor. Referring first to
FIG. 49
, a thermal oxide film (not shown) and a CVD nitride film
221
are deposited in this order on silicon substrate
220
, and then CVD nitride film
221
and the thermal oxide film are patterned. Using CVD nitride film
221
and the oxide film thus patterned as a mask, silicon substrate
220
is subjected to anisotropic etching to form a silicon island
220
a
. Thereafter a thermal oxide film (not shown) is formed at a surface of silicon substrate
220
by thermal oxidation process. After the CVD nitride film is deposited at the entire surface, the entire surface of the silicon nitride film is etched back by anisotropic RIE (Reactive Ion Etching).
Referring to
FIG. 50
, a silicon nitride film
223
remains at a sidewall of silicon island
220
a
after etching back the entire surface. Then, silicon substrate
220
is isotropically etched using CVD nitride film
221
and sidewall nitride film
223
as a mask. Such isotropic etching removes a desired amount of the surface of substrate
220
exposed from nitride films
221
and
223
. The substrate is then subjected to long-time thermal oxidation process at a high temperature of, for example, 1100° C.
Referring to
FIG. 51
, through such thermal oxidation process a field oxide film
211
is formed on silicon substrate
220
and monocrystalline silicon layer
203
is formed on field oxide film
211
, and then CVD nitride film
221
and sidewall nitride film
223
are removed. A sacrifice oxide layer is once formed at a surface of monocrystalline silicon layer
203
through thermal oxidation process in order to remove damage on the surface of monocrystalline layer
203
, and this sacrifice oxide layer is then removed by hydrofluoric acid or the like.
Referring to
FIG. 48
, after a gate insulating layer is formed a gate electrode layer
207
is formed to face a region of monocrystalline silicon layer
203
to serve as a channel with the gate insulating layer interposed therebetween. Impurities are introduced using gate electrode layer
207
and the like as a mask to form source/drain regions
203
a
and
203
b
at monocrystalline silicon layer
203
, thereby completing a thin film transistor with the DELTA structure.
Thus, since monocrystalline silicon layer
203
serving as a channel has width W
2
smaller than height H
2
and is covered with gate electrode
207
on both sides in the conventional thin film transistor, the transistor has great current drivability and its characteristics is less degraded by reduction in length of the channel. In addition, gate electrode
207
covers both side surfaces and an upper surface of monocrystalline silicon layer
203
and width W
2
of a lower surface is small, so that the region serving as a channel is covered with gate electrode layer
207
for the most part. As a result, the conventional thin film transistor can also prevent electric effects imposed by external electrode interconnections. Therefore, the conventional thin film transistor is extremely advantageous for use as a transistor surrounded by many interconnections such as a load transistor forming a memory cell of an SRAM (Static Random Access Memory).
However, since monocrystalline silicon layer
203
has a small width W
2
, the conventional thin film transistor cannot make a contact with another conductive layer in a stable manner. This problem will be described in detail below.
FIG. 52
shows an example of the structure of the thin film transistor connected to an upper conductive layer. Referring to
FIG. 52
, an upper conductive layer
218
is connected to the portion of monocrystalline silicon layer
203
to serve as a source/drain region through a contact hole
217
a
provided in an interlayer insulating layer
217
. Contact hole
217
a
is generally formed by etching interlayer insulating layer
217
using a resist pattern
219
formed on interlayer insulating layer
217
as a mask as shown in FIG.
53
. However, a hole pattern
219
a
of resist pattern
219
may be shifted in the direction of X shown in the figure due to overlay displacement of the mask or the like during photolithography for forming resist pattern
219
.
Since monocrystalline silicon layer
203
has width W
2
as small as 0.2 &mgr;m, contact hole
217
a
is easily shifted away from monocrystalline silicon layer
203
as shown in FIG.
54
. Consequently, a contact between upper conductive layer
218
and monocrystalline silicon layer
203
cannot be made.
Furthermore, the conventional method of manufacturing a thin film transistor requires long-time thermal oxidation process at a high temperature for forming an SOI structure. If such long-time thermal oxidation process at a high temperature is carried out after other elements are formed, they may be destroyed by diffusion of impurities or the like. Therefore, such high temperature, long-time thermal oxidation process must be carried out before other elements are formed. As a result, there is another problem that this thin film transistor cannot be formed over other elements formed on silicon substrate
220
.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a thin film transistor that allows a contact between a source/drain region of a thin film transistor and an upper or lower conductive layer to be made stably.
Another object of the present invention is to provide a method of manufacturing a thin film transistor allowing a thin film transistor to be formed over an element formed at a substrate.
A semiconductor device having a thin film transistor according to one aspect of the present invention includes first and second conductive layers, a semiconductor layer, and a gate electrode layer. The first and second conductive layers are formed isolated from each other. The semiconductor layer has one end placed on top of the first conductive layer and in contact with the first conductive layer and the other end placed on top of the second conductive layer and in contact therewith. The gate electrode layer covers an upper surface and opposing side surfaces of the semiconductor layer, with a gate insulating layer interposed therebetween, at a central portion sandwiched by one and the other ends of the semiconductor layer. The line width defined by the opposing side sur
Ipposhi Takashi
Iwamatsu Toshiaki
Maegawa Shigeto
McDermott & Will & Emery
Rose Kusha
Zarabian Amir
LandOfFree
Semiconductor device having a thin film transistor and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having a thin film transistor and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a thin film transistor and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3331758