Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-04-25
2002-12-17
Ho, Hoai V. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C438S011000, C438S014000, C438S015000, C438S018000
Reexamination Certificate
active
06495856
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a diagnosing technology for a semiconductor device and, more particularly, to a semiconductor device and a method for testing a semiconductor device for short-circuits.
DESCRIPTION OF THE RELATED ART
A short-circuit is fatal to semiconductor devices, and lowers the production yield. When the short-circuit is detected in a semiconductor device, it is important for the manufacturer to investigate the cause of the short-circuit. One of the approaches to the cause of the short-circuit is a direct observation on the short-circuit. Conventionally, an optical microscope was used in the direct observation. The design rule has been severe, and the conductive lines are presently arranged at high dense on a semiconductor chip. In this situation, it is hard to observe the conductive lines directly with the optical microscope. Moreover, a possible portion of the short-circuit is merely detected through the direct observation with the optical microscope. The short-circuit is to be confirmed through an electric test. This results in a large amount of time and labor consumed for the diagnosis.
In order to make the test simple, it is proposed to test a semiconductor device with a scanning electron beam microscopy. A typical example of the testing method using the scanning electron beam microscopy is disclosed in Japanese Patent Publication of Unexamined Application No. 4-314032.
FIG. 1
shows a substrate
106
for an array of thin film transistors. Gate lines
107
and source lines
108
are laid on a lattice pattern, and the gate lines
107
are electrically isolated from the source lines
108
.
The prior art testing method is based on the charge-up phenomenon in the insulating during the observation with the scanning electron beam microscopy, and the array of thin film transistors is tested as follows. First, the substrate
106
is fixed to the sample table of the scanning electron beam microscopy, and is electrically isolated. Conductive tapes
103
and
109
are adhered to the substrate
106
. The conductive tape
109
extends over the gate lines
107
, and the gate lines
107
are short-circuited. On the other hand, the conductive tape
103
extends over the source lines
108
, and the source lines
108
are short-circuited. A switching unit
101
is connected between the conductive tape
109
and a ground line
102
for the gate lines
107
, and another switching unit
104
is connected between the conductive tape
103
and a ground line
105
for the source lines
108
.
An analyst checks the array of thin film transistors to see whether or not any gate line
107
is short-circuited with the source lines
108
at the overlapped portions therebetween as follows. First, the analyst turns on the switching unit
101
, and turns off the other switching unit
104
. The gate lines
107
are grounded through the conductive tape
109
and the switching unit
101
, and the source lines
108
are electrically isolated from the ground line
105
. Subsequently, the source lines
108
are charged. The source lines
107
are designed to be electrically isolated from the gate lines
108
. Therefore, if the source lines
107
are surely isolated from the gate lines
107
, the charge-up phenomenon takes place at all the overlapped portions. However, if a source line
108
is short-circuited with the gate line
107
, the overlapped portion is never charged. The short-circuit is detectable on the basis of the difference between the charge-up portions and non-charged portion.
FIG. 2
shows a test pattern formed in a semiconductor device to be tested through another prior art method. The prior art method is disclosed in IEEE TRANSACTION ON SEMICONDUCTOR MANUFACTURING, pages 384-389, 1997. Conductive pads
201
are arranged on a semiconductor substrate, and a test pattern
202
is formed among the conductive pads
201
. The test pattern
202
is connected through a conductive buried-layer and a diffused region (not shown) to the semiconductor substrate or the ground
203
. The semiconductor substrate is placed in vacuum, and is scanned with an electron beam. When the conductive pads
201
are radiated with the electron beam, secondary electrons are generated. The amount of secondary electrons is measured. If a conductive pad
201
is short-circuited with the test pattern due to an improper pattern transfer, the amount of secondary electrons is reduced. Thus, the analyst checks the dispersion of the secondary electrons to see whether or not a short-circuit takes place.
A semiconductor dynamic random access memory device is designed under the most severe design rules. The semiconductor dynamic random access memory cell is implemented by a series combination of an access transistor and a storage capacitor. In case where a stacked storage capacitor is employed in the dynamic random access memory device, miniature capacitor electrodes are arrayed on an inter-layered insulating layer at high dense, and a short-circuit is liable to take place between the adjacent miniature capacitor electrodes. The stacked storage capacitor is so small that a miniature short-circuit affects the data holding characteristics of the dynamic random access memory cell. However, such a miniature short-circuit is hardly observed with the scanning electron beam microscopy, because the image of miniature short-circuit is affected by noise due to fluctuation of the device pattern.
The above-described prior art detecting technologies have the following problems. Only the short-circuit between the conductive lines connected through the conductive tapes
103
/
109
is detectable through the first prior art testing method shown in FIG.
1
. Even if a short-circuit takes place between the conductive line
107
/
108
and an isolated conductive piece, the analyst can not specify the short-circuit through the first prior art testing method shown in FIG.
1
. When the analyst checks the array of stacked capacitor electrodes for a short-circuit, he or she needs to prepare a lot of miniature conductive tapes and micro-switches, and adheres the miniature conductive tapes between the stacked capacitor electrodes of all the combinations. It is not feasible. Therefore, the first prior art method is not applicable to the array of stacked capacitor electrodes.
On the other hand, the test pattern
202
consisting of conductive lines is required for the second prior art testing method shown in FIG.
2
. The test pattern
202
is formed on the semiconductor chip for the testing use only, and the test pattern
202
render the layout between the conductive pads
201
and the test pattern
202
different from the actual layout of the conductive pads
201
. When the second prior art testing method is applied to the array of stacked capacitor electrodes, a test pattern is to be formed in the array of stacked capacitor electrodes. However, the stacked capacitor electrodes are patterned under the most severe design rules. Therefore, it is impossible to form the test pattern in the array of stacked capacitor electrodes. In other words, the second testing method is available for an array of conductive pieces not patterned under the most severe design rules.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a method for testing a semiconductor device for a short-circuit in an array of miniature conductive pieces.
It is another important object of the present invention to provide a semiconductor device, which is to be tested through the testing method.
To accomplish the object, the present invention proposes to form a miniature test pattern same as a conductive pattern to be test.
In accordance with one aspect of the present invention, there is provided a semiconductor device fabricated on a substrate comprising an insulating layer formed over a major surface of the substrate, conductive strips laid on a pattern on the insulating layer and incorporated in an electric circuit, and test conductive strips laid on at least a part of the pattern on the insulating layer concurrently
Choate Hall & Stewart
Ho Hoai V.
Huynh Andy
NEC Corporation
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