Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Patent
1997-03-19
2000-02-22
Williams, Alexander Oscar
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
257737, 257738, 257700, 257758, 257668, 257701, 361792, 174255, 174524, H01L 2348, H01L 2352, H05K 100, H05K 720
Patent
active
060283645
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a semiconductor device of the type used for high density packaging, a multi-chip module, bare chip packaging, and the like, and a packaging structure of the semiconductor device.
BACKGROUND ART
In recent years, the reduced sizes and increased performances of electronic devices have generated a demand for higher integration, higher density, and higher processing speed in the semiconductor devices used for such electronic devices. To meet such a demand, packages for semiconductor devices are being developed from a pin insertion type to a surface packaging type for purposes of increasing the packaging densities thereof, and also developments have been proposed for a DIP (Dual Inline Package) type to a QFP (Quad Flat Package) type and a PGA (Pin Grid Array) type package for coping with the requirements of a multi-pin arrangement.
Of the packages thus developed, the QFP type makes it difficult to cope with a multi-pin arrangement because it is so configured that leads to be connected to a packaging substrate are concentrated only at a peripheral portion of the package when they are also liable to be deformed due to the small diameter thereof. On the other hand, the PGA type has a limitation in that it presents difficulties in coping with both high speed processing and surface packaging because it is so configured that the terminals to be connected to a packaging substrate are elongated and very collectively arranged.
Recently, to solve these problems and to realize a semiconductor device capable of coping with high speed processing, a BGA (Ball Grid Array) package has been disclosed in U.S. Pat. No. 5,148,265, which has ball-like connection terminals over the entire packaging surface of a carrier substrate electrically connected to a semiconductor chip by gold wire bonding. In this package, since the terminals to be connected to a packaging substrate are formed into ball-like shapes, they can be arranged in a dispersed manner over the entire packaging surface without experiencing the deformation of leads as found in the QFP, so that the pitches between the terminals become larger, to thereby make surface packaging easy; and also, since the lengths of the connection terminals are shorter than those of the type package, the an inductance component becomes smaller and thereby the signal transmission speed becomes faster, with a result that such a package is amenable to high speed processing.
In the above-described BGA package, an elastic body is inserted as a component between a semiconductor chip and terminals of a packaging substrate for relieving thermal stress produced due to a difference in thermal expansion between the packaging substrate and the semiconductor chip upon packaging thereof. The semiconductor device having such a structure, however, has problems related to on the use of gold wire bonding for connection with upper electrodes of the semiconductor chip; namely, since the connection portions connected to the gold wires are concentrated only at a peripheral portion of the chip, the structure has an inherent limitation to the increasing future demand for a multi-pin arrangement, and a higher processing speed for the semiconductor devices, and the structure also provides an inconvenience in terms of mass-production and any improvement in production yield because of the increased number of production steps due to the complexity thereof.
Japanese Patent Laid-open No. Hei 5-326625 discloses an improved packaging structure for a flip-chip type package in which a LSI chip having solder bumps is mounted on a multi-layered wiring ceramic substrate having solder bumps, wherein a sealing member is filled between the LSI chip and the multi-layered wiring ceramic substrate as a carrier substrate. The above packaging structure, however, seems to have a problem in terms of higher density interconnection, higher response speed of signals, and miniaturization of the package, because the use of the ceramic substrate as multiple wiring layers makes it difficult to r
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Akahoshi Haruo
Anjou Ichirou
Eguchi Shuji
Ishii Toshiaki
Miwa Takao
Hitachi , Ltd.
Williams Alexander Oscar
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