Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-10-20
2001-04-24
Crane, Sara (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S637000, C438S656000, C438S658000, C438S663000, C438S664000, C438S672000, C438S675000, C438S682000, C438S683000, C257S741000, C257S748000, C257S750000, C257S754000, C257S755000, C257S757000, C257S758000, C257S760000, C257S763000
Reexamination Certificate
active
06221760
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor device having a silicide structure and, more particularly to an improved silicide structure using a semi-insulating polycrystalline silicon film. The present invention also relates to a method for manufacturing the same.
(b) Description of the Related Art
Recently, a shallow junction structure is a key technology in a diffused region of small sized and high density semiconductor devices. In the shallow junction structure, some problems are reported in connection with the contacts between diffused regions and overlying metallic interconnects.
FIGS. 1A
to
1
D show a semiconductor device in consecutive fabrication steps thereof, which is proposed for solving the above mentioned problems by Y. Taur, S. Cohen, S. Wind et al., in “International Electron Device Meeting Technical Digest (IEDM)”, pp901, 1192.
In
FIG. 1A
, a field oxide film
302
is formed on a silicon substrate
301
, followed by formation of an oxide film and a polycrystalline silicon (polysilicon) film. After an electron beam (EB) exposure, a reactive ion etching using a HBr/Cl
2
etching gas is conducted at a high selectivity between the silicon substrate and the silicon oxide film to form a gate structure including a gate oxide film
303
and a gate polysilicon film
304
, thereby obtaining 0.1 micron-order gate length for a MOSFET.
Subsequently, Sb ions are introduced to the surface portions of the silicon substrate to make the surface portions of the silicon substrate
301
amorphous, followed by ion-implantation with BF
2
ions
316
having a low acceleration energy, and forming p+ extensions
317
having a depth as low as 50 to 70 nanometers (nm), as shown in FIG.
1
A. The p+ extension
317
functions for alleviating difficulties in forming contacts between the diffused regions and overlying metallic interconnects as well as reducing the contact resistance therebetween.
Thereafter, as shown in
FIG. 1B
, an oxide film is deposited, followed by etch-back thereof to form a side-wall
305
. A selective ion-implantation of silicon surface with impurity ions
318
is then effected to form source/drain regions
319
having a depth larger than the depth of the p+ extensions
317
. A blanket Ti film
310
is then deposited on the entire surface by sputtering, as shown in FIG.
1
C.
Thereafter, a sintering is conducted to form a TiSi film
311
at the interface between the source/drain region
319
and the Ti film
310
. An interlayer dielectric film
309
is then deposited, followed by dry-etching thereof to form via-holes (through-holes). Sputtering and subsequent etching of AlSiCu, for example, provide metallic interconnects
312
in the semiconductor device, as shown in FIG.
1
D.
In the proposed process, the shallow p+ extensions
317
enables fabrication of 0.1-micron order small-sized transistors with an enough process margin for the contacts between the heavily doped regions
319
and the metallic interconnects
312
.
However, there is a possibility that the doped impurity ions diffuse in the lateral direction as well as the vertical direction during the thermal treatment for activation of the impurity ions in the heavily doped source/drain regions
319
. The lateral diffusion generally demands a large thickness of the side-wall
305
in the gate structure for assuring the presence of the shallow p+ extensions
317
, which hinders a smaller gate length in the gate structure. Moreover, the silicide structure employed for reducing the resistance of the diffused regions
319
and metallic interconnects
312
tends to cause a leakage current flowing between the gate electrode and the source/drain regions due to an inaccurate positioning of etching or diffusion.
FIGS. 2A
to
2
D show, similarly to
FIGS. 1A
to
1
B, a second conventional fabrication process, proposed by H. Kotaki, M. Nakano, Y. Takegawa et al. in “International Electron Device Meeting Technical Digest (IEDM)”, pp839, 1993. A field oxide film
402
is formed on a silicon substrate
401
, followed by formation of gate oxide film
403
, gate polysilicon film
404
and side-wall
405
. The resultant wafer is introduced into a Load-Lock chamber of a LPCVD equipment, wherein N
2
gas having a dew point of −100° C. flows, while controlling the equipment so that a native oxide film or water molecules are not attached to the surface of the wafer.
A Si film
420
is then deposited thereon by using a SiH
4
gas at a substrate temperature of 620° C., as shown in FIG.
2
A. In this step, a Si epitaxial layer is formed on the surface of the silicon substrate
401
due to the clean surface thereof, whereas a polysilicon film is formed on the oxide films
402
and
405
.
A selective etching for the polysilicon film by using an etchant containing HNO
3
and CH
3
COOH leaves the elevated Si epitaxial layer
421
formed on the surface of the silicon substrate
401
, as shown in FIG.
2
B. An ion-implantation with impurity ions
418
and subsequent activation heat treatment are then conducted to provide a shallow diffused layer
422
, followed by sputtering to form a Ti film
410
thereon, as shown in FIG.
2
C.
A TiSi film
411
is then selectively formed on the surface of the Si epitaxial layer
421
, followed by deposition of a blanket interlayer dielectric film
409
and subsequent selective dry-etching thereof to form via-holes. Then, sputtering and subsequent patterning of a metal such as AlSiCu is effected to form metallic interconnects
412
having via-plugs formed in the via-holes, as shown in FIG.
2
D.
In the second conventional process as described above, the elevated Si epitaxial source/drain regions
421
provide advantages of suppression of the transistor short-channel effect in the shallow source/drain regions, reduction of resistance in the diffused regions and via-plugs due to the metallic silicide layer, and a larger process margin between the heavily doped source/drain regions and the metallic interconnects.
In a small-sized semiconductor device formed by the second conventional technique, the epitaxial step for the elevated epitaxial source/drain regions involves contamination at the interface between the elevated epitaxial regions and Si substrate in a small-sized semiconductor device formed on a larger wafer, which requests a surface treatment at the interface between the epitaxial layer and the silicon substrate during the growth step. The second conventional process also requests a high selectivity between the polysilicon film and the monocrystalline silicon substrate, which is difficult to achieve in mass production.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device having shallow diffused regions, low contact resistance between the shallow diffused regions and metallic interconnects, and capable of allowing a sufficient process margin between the diffused regions and the metallic interconnects in the fabrication process.
It is another object of the present invention to provide a method for fabricating such a semiconductor device.
The present invention provides a semiconductor device comprising a semiconductor substrate, a first dielectric film formed on the semiconductor substrate, a diffused region formed in a surface region of the semiconductor substrate, a semi-insulating polycrystalline silicon (SIPOS) film formed at least on the diffused region and the first dielectric film, a second dielectric film formed on the SIPOS film and having a via-hole above the diffused region, and a metallic film formed on the second dielectric film and having a via-plug filling the via-hole, the SIPOS film forming at a bottom of the via-plug a metallic silicide made from the metallic film and SIPOS film for electrically connecting the via-plug and the diffused region.
The present invention also provides a method for manufacturing a semiconductor device comprising the steps of forming a diffused region in a surface region of a semiconductor substrate, forming a
Crane Sara
Hayes, Soloway, Hennessey Grossman & Hage, P.C.
NEC Corporation
Souw Bernard E.
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