Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-15
2004-11-16
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S409000
Reexamination Certificate
active
06818943
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a method of fabricating the same. More particularly, it relates to semiconductor device suitably applicable to a nonvolatile semiconductor memory in which a floating gate and a control gate are formed via a dielectric film.
2. Description of the Related Art
Recently, a nonvolatile memory such as an EEPROM which holds stored data even when disconnected from a power supply has attracted attention as a semiconductor memory. In this nonvolatile memory, a floating gate is formed on a semiconductor substrate via a tunnel insulating film, and a control gate is formed as to oppose this floating gate via a dielectric film.
One example of this nonvolatile semiconductor memory is disclosed in Japanese Patent Laid-Open No. 6-85279. This element is obtained by turning the above nonvolatile semiconductor memory upside down. More specifically, this nonvolatile semiconductor memory is fabricated by sequentially stacking a gate insulating film, a floating gate, and a tunnel insulating film in an insulating film formed on a semiconductor substrate, and forming a semiconductor layer having a source and a drain on top of the resultant structure. Since contacts can be extracted from the upper surface side, this element facilitates arranging word lines and is suited to increase the degree of integration.
The structure, however, of this nonvolatile semiconductor memory is complicated because the memory has a stacked gate structure, and this extremely increases the accuracy requirements when the element is to be formed. In addition, to lower the write voltage, it is necessary to increase the area of the overlap of the control gate and the floating gate. This not only increases the number of fabrication steps and the fabrication cost and lowers the reliability but also interferes with an increase in the degree of integration.
To solve the above problems, Japanese Patent Laid-Open No. 59-155968 or Japanese Patent Publication No. 7-112018 has disclosed an EEPROM which has a small cell area and includes a single-layer polysilicon film. This EEPROM includes a first element active region formed by forming a source and a drain on a semiconductor substrate and a second element active region formed adjacent to the first element active region via an element isolation structure by forming an impurity diffusion layer. A single-layer polysilicon film is patterned to form a floating gate which Is formed by patterning on a channel between the source and the drain via a tunnel insulating film in the first element active region. This floating gate is formed by patterning to oppose the impurity diffusion layer via a gate insulating film in the second active region. The impurity diffusion layer in the second element active region functions as a control gate.
In the above single-layer gate EEPROM, however, it is necessary to apply a high voltage of 20 (V) or more to the control gate, i.e., the impurity diffusion layer when data is erased or written, especially when data is erased. Consequently, it becomes difficult to ensure a large enough breakdown voltage between the control gate and the semiconductor substrate, leading to a serious problem of an operation error.
Furthermore, Japanese Patent Laid-Open No. 7-147340 has disclosed an EEPROM which has a diffusion layer serving as the control gate separated from other semiconductor area to apply a high voltage to the diffusion layer.
However, it is difficult to minimize variations in the threshold value of the EEPROM and stably perform write and read operations.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a reliable semiconductor device which is a single-layer gate semiconductor device by which a low-cost process is possible, has a control gate which can well withstand a high voltage applied when data is erased or written, and can prevent an operation error, and a method of fabricating the same.
A semiconductor device of the present invention is a semiconductor device comprising a semiconductor substrate in which a first and a second element active regions are demarcated by means of element isolation structure, structure having a shield plate electrode formed on the semiconductor substrate via a first insulating film, a first and a second conductive regions formed on a surface region of the semiconductor substrate in the first element active region, a first electrode formed on the semiconductor substrate between the first and the second conductive regions via a second insulating film, a third conductive region formed in the surface region of the semiconductor substrate in the second element active region, and a second electrode formed on the third conductive region via a dielectric film. The first electrode and the second electrode are electrically connected.
Another aspect of the semiconductor device of the present invention is a semiconductor device comprising a semiconductor substrate in which a first and a second element active regions are demarcated by means of element isolation structure, a first and a second conductive regions formed on a surface region of the semiconductor substrate in the first element active region, a first electrode formed on the semiconductor substrate between the first and the second conductive regions via a second insulating film, a third conductive region formed in the surface region of the semiconductor substrate in the second element active region, and a second electrode formed on the third conductive region via a dielectric film. The first electrode and the second electrode are electrically connected and a third electrode is connected to the semiconductor substrate to apply a predetermined electric potential to the semiconductor substrate in the first element active region.
A method of fabricating a semiconductor device of the present invention comprises the first step of defining first, second, third, and fourth element active regions by forming an element isolation structure on a semiconductor substrate having an insulating layer in a predetermined depth and covering a region from side surfaces to a lower surface of at least the first element active region with the insulating layer and the element isolation structure the second step of forming a first diffusion layer by doping an impurity into said first element active region, the third step of forming a diffusion layer region by doping an impurity having a conductivity type opposite to a conductivity type of the semiconductor substrate into a surface region of the semiconductor substrate in the second element active region, the fourth step of forming first, second, third, and fourth insulating films on the semiconductor substrate in the first, second, third, and fourth element active regions, respectively, the fifth step of forming a conductive film via first, second, third, and fourth insulating films on an entire surface of the semiconductor substrate in the first, second, third, and fourth element active regions, respectively, the sixth step of patterning the conductive film to leave a predetermined pattern in at least one of the first and third element active regions and form gate electrodes in the second and fourth element active regions, the seventh step of doping an impurity into the third and fourth element active regions to form a pair of second diffusion layers and a pair of third diffusion layers in surface regions of the semiconductor substrate on two sides of the conductive film in the third and fourth element active regions, the eighth step of doping an impurity having a conductivity type opposite to a conductivity type of the diffusion layer region into the second element active region to form a pair of fourth diffusion layers in surface regions of the semiconductor substrate on two sides of the conductive film in the second element active region, the ninth step of forming a fifth diffusion layer by doping an impurity into the semiconductor substrate near the third element active region, and the tenth step of forming an el
Connolly Bove & Lodge & Hutz LLP
Nippon Steel Corporation
Vu Hung
LandOfFree
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