Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2006-07-31
2009-10-13
Abraham, Esaw T (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S758000, C714S763000, C365S201000, C365S232000
Reexamination Certificate
active
07603592
ABSTRACT:
A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.
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Akiyama Satoru
Hanzawa Satoru
Kajigaya Kazuhiko
Sekiguchi Tomonori
Takemura Riichiro
Abraham Esaw T
Elpida Memory Inc.
Hitachi , Ltd.
Miles & Stockbridge P.C.
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