Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1998-03-27
2004-06-15
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S162000
Reexamination Certificate
active
06750086
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device such as a liquid crystal display (LCD), and more particularly to an LCD of the integrated-driver-circuit type in which a thin film transistor (TFT) using a polycrystalline semiconductor layer is formed in the display section and the peripheral section. The also invention relates to a method of manufacturing such a semiconductor device.
2. Description of the Related Art
In recent years, liquid crystal display systems (LCD) have been increasingly put into practice in the office automation and audio-visual equipment industries in view of the significant advantages of downsizing and reduced equipment requirements, as well as reduced power consumption. In particular, an active-matrix-type LCD, in which TFTs are arranged in a matrix, each acting as a switching element for controlling the timing for overwriting image information in the individual pixel, enables a huge-size display screen and a high-resolution animation display and is hence used as a high-quality display system for various types of television sets and personal computers.
A TFT is a field effect transistor (FET) which can be obtained by forming a semiconductor and a metal layer in a predetermined island pattern over an insulating substrate. In an active-matrix-type LCD, a pair of pixel capacitors for driving liquid crystal are respectively formed on a pair of substrates between which the liquid crystal is sandwiched, and a TFT is connected to one electrode of each pixel capacitor.
Attempts have been made to improve the performance of LCDS. To this end, an LCD has been developed in which a polysilicon (p-Si) film is used as a substitute for amorphous silicon (a-Si) film, which has been widely used in various conventional LCDS, and annealing using laser beam irradiation is carried out for formation or growth of p-Si grains. Generally, p-Si is high in mobility compared to a-Si so that TFT can be downsized, thus realizing a high aperture ratio and a high resolution. Further, since high speed TFT can be achieved due to the gate-self-align structure and the reduced parasitic capacitance, it is possible to obtain a high-speed driver circuit by forming CMOS comprising n-channel TFT and p-channel TFT. It is therefore possible to realize a reduced manufacturing cost and downsizing of the LCD module.
To form the p-Si film on an insulating substrate, it has currently been customary 1) to recrystallize the a-Si film, which has been formed at low temperature, by annealing at high temperature, or 2) to employ solid phase growth at high temperature. In either case, since the process is subject to a relatively high temperature in excess of 900° C., a quartz glass substrate is needed as the insulating substrate in view of its high heat-resistance although there is the drawback that it is expensive. In the meantime, an alternative method employing laser-annealing has been developed in which silicon crystallization is carried out at a relatively low substrate temperature not exceeding 600° C. so as to be able to use an inexpensive alkaliless glass as the insulating substrate. The fabrication process whose process temperature does not exceed 600° C. throughout all of the steps of manufacturing the TFT substrate is called the low-temperature process , and is essential to mass production of low-price LCDs.
A silicon film to be formed on such an insulating substrate would not be a single crystal film but usually takes on an amorphous or a polycrystalline structure. These non-single crystal silicon film contains a large number of dangling bonds which do not bond covalently. Such dangling bonds have a trap level in the forbidden band. Since electrons are caused to move between the valence band and the conduction band via the trap level, a transistor using such a film would be high in on resistance and low in off resistance and hence low in on-off ratio. To solve this problem, it is currently known to terminate the dangling bonds with hydrogen atoms. Namely, hydrogen gas activated during or after formation of the non-single-crystal silicon is introduced to link hydrogen atoms with the dangling bonds, thereby causing the trap levels to disappear.
FIG. 1
of the accompanying drawings is a cross-sectional diagram showing a sectional structure of such a p-Si TFT; on the left side is an n-channel TFT and on the right side is a p-channel TFT. On a substrate
10
, a gate electrode
11
of metal such as chromium is formed and a gate insulation film
12
of, for example, silicon nitride (SiN
N
) and/or silicon oxide (SiO
2
) is formed so as to cover the gate electrode
11
. A p-Si film
23
is formed on the gate insulation film
12
. For the n-channel TFT, this p-Si film
23
has a lightly doped region LD containing n-type impurities at a low density (N
−
) utilizing the edge of an implantation stopper
14
of SiO
2
patterned in the shape of the gate electrode
11
on the p-Si film
23
, and source and drain regions S, D located outside the lightly doped region LD and containing the n-type impurity at a high density (N
+
),. For the p-channel TFT, source and drain regions
23
S,
23
D contain p-type impurities at a high density (P
+
). In either of the n- and p-channel TFTs, an intrinsic layer substantially devoid of impurities and serving as a channel region CH is located beneath the implantation stopper
14
. Further, an interlayer insulation film
15
such as SiN
N
is formed so as to cover these regions of the p-Si film
23
, and on the interlayer insulation film
15
, source and drain electrodes
16
,
17
of metal are formed and are connected to the source and drain regions
23
S,
23
D, respectively, via contact holes in the interlayer insulation film
15
. In the pixel region, a non-illustrated liquid-crystal-driving electrode in the form of a transparent conductive film such as indium tin oxide (ITO) is formed on the interlayer insulation film
18
covering the source and drain electrodes
16
,
17
and is connected to the source electrode
16
.
In the n-channel TFT, the structure having the LD region
23
LD located between the source and drain regions
23
S,
23
D and the channel region CH is called an LDD (lightly doped drain). In an LCD, such an LDD structure is employed for the purpose of controlling the off current. As an alternative, a double gate structure in which the gate electrode
11
and the channel region CH are formed in series may be employed with the same result.
The channel regions CH may be doped with different impurities, whose conduction types are opposite to conduction type of each TFTS, before the above-mentioned impurity implantation; the resulting TFT is called a channel-dope type TFT.
The fabrication process of this TFT will now be described. Firstly, on a relatively low heat-resisting substrate
10
such as alkaliless glass, a gate electrode
11
is formed by sputtering chromium and then etching the chromium film, whereupon a gate insulation film
12
is continuously formed of silicon nitride (SiN
N
) and silicon oxide (SiO
2
) as well as amorphous silicon (a-Si) by plasma CVD, without breaking the vacuum at all. Hydrogen in a-Si, which prevent crystallization, is then removed by dehydrogenation annealing, whereupon a polysilicon (p-Si) film
23
is formed by polycrystallizing a-Si at a temperature not exceeding the resisting temperature of the substrate
10
using excimer laser annealing (ELA). Further, a silicon oxide (SiO
2
) film is formed over the p-Si film
23
and then a positive photoresist is formed over the SiO
2
film, whereupon the photoresist is exposed to light irradiation from the substrate side, which is so-called reverse side exposure. As the result of this reverse side exposure, the photoresist is photosensitized in such a manner that a pattern reflecting the shadow of the pattern shape of the gate electrode
11
is inverted. Subsequently, the photoresist is developed, and then with the resulting photoresist as a mask, the insulation film is etched to form the implantation sto
Hirai Kyoko
Jinno Yushi
Morimoto Yoshihiro
Nakanishi Shiro
Yamada Tsutomu
Hogan & Hartson LLP
Niebling John F.
Pompey Ron
Sanyo Electric Co,. Ltd.
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