Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2002-03-12
2004-04-06
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S782000, C257S700000
Reexamination Certificate
active
06717278
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device in which a resist is formed on wiring patterns on a substrate and, a semiconductor chip is die-bonded onto the resist.
2. Description of the Prior Art
In a conventional such a kind of semiconductor device
1
shown in FIG.
7
(A), a resist
4
is formed on a substrate
3
provided with wiring patterns
2
, and a semiconductor chip
6
is die-bonded onto the resist
4
via a die-bonding sheet
5
. Furthermore, an upper surface electrode
6
a
of the semiconductor chip
6
and a bonding pad
2
a
of the wiring patterns
2
are wire-bonded with each other by a gold wire
7
, and the semiconductor chip
6
and the gold wire
7
are encapsulated by a molding resin
8
.
In such the semiconductor device
1
, although the resist
4
is to fill a space between the substrate
3
and the die-bonding sheet
5
, a formed position thereof was not especially taken into account.
In the prior art, since the formed position of the resist
4
was not especially taken into account, there was a case a visible outline of the resist
4
comes close to and arranged in parallel to the wiring patterns
2
as shown in an A portion in FIG.
7
(B). Then, in this case, there was a fear that a flow-out of a periphery edge portion B of the resist
4
onto the wiring patterns
2
partly causes a plating defect and thus, a short-circuit of the wiring patterns
2
.
More specifically, if the resist
4
flows onto the wiring patterns
2
, a resist thin film
4
a
having a number of pinholes is formed in a long thin manner on the wiring patterns
2
, and therefore, in a following plating processing, a portion of the wiring patterns
2
being exposed to the pinholes is also plated, and the plating becomes a long thin plating film on the surface of the resist thin film
4
a
. However, since the long thin plating film is connected to the wiring patterns
2
through the pinholes only, there was a fear that the long thin plating film is easily released due to a vibration, and therefore, there is a possibility that the wiring patterns
2
is short-circuited out by the released plating film.
SUMMARY OF THE INVENTION
Therefore, it is a primary object of the present invention to provide a semiconductor device capable of preventing a short-circuit of wiring patterns.
A semiconductor device according to the present invention comprises: a substrate formed with wiring patterns on its upper surface; a plurality of througholes formed in a matrix fashion on the substrate; a resist formed on the upper surface of the substrate; a semiconductor chip die-bonded onto the resist; a mold which encapsulates the semiconductor chip; and an electrode connected to one ends of the wiring patterns through the througholes from an lower surface of the substrate, wherein an outer peripheral edge line of the resist passes over the througholes.
Since the plurality of througholes are formed in a matrix fashion on the substrate, it is impossible to make a direction to which each of the wiring patterns extends from each of the througholes coincident a direction that the througholes are aligned due to an obstruction of adjacent througholes. That is, the direction to which the wiring patterns extend from the througholes is sure to form a predetermined angle with respect to the direction to which the througholes are aligned. Accordingly, in the present invention in which the outer peripheral edge line of the resist passes over the througholes, the outer peripheral edge line of the resist never comes close to and be in parallel to the wiring patterns, and there is no possibility that a plating film is formed in a long thin shape on the resist flowing-out onto the wiring patterns.
According to the present invention, it is possible to prevent a short-circuit of the wiring patterns due to an exfoliation of the plating film, and it is possible to drastically reduce a fraction defective.
The above described objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5874784 (1999-02-01), Aoki et al.
patent: 5953592 (1999-09-01), Taniguchi et al.
patent: 6198165 (2001-03-01), Yamaji et al.
Kishimoto Ichirou
Miyata Osamu
LandOfFree
Semiconductor device having a resist edge positioned over... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having a resist edge positioned over..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a resist edge positioned over... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3245412