Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2002-02-25
2003-12-23
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S287000, C438S303000, C438S595000, C438S591000
Reexamination Certificate
active
06667199
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and its manufacturing method and especially, relates to the semiconductor having a field effect transistor and its manufacturing method.
An integrated-circuit fabrication technology using silicone continues making progress at a tremendous speed. The advancement of a micro-fabrication technology has reduced element sizes and enabled the integration of an additional number of elements onto one chip, resulting in an increase in functionality. At the same time, the advanced element micro-fabrication technology has improved their current driving performance while reducing load capacity, achieving higher processing speeds.
As the element sizes have increasingly became small, the thickness of the gate insulating film has been also made thinner. Although the sizes of entire elements may be further made smaller, the thickness of the insulating film made of silicone dioxide, which is the material used for conventional films, virtually has been reduced to its critical limit. The thickness of the thinnest one of existing silicone-dioxide gate insulating films is about 2 nm and making the silicone-dioxide films further thinner may cause a direct tunnel effect, leading to a large leak current. The presence of a large leak current not only increases power consumption but also decrease the number of charges induced in the reverse layer of a channel, which in turn, deteriorates the element's current driving performance. Moreover, since such a thin silicone dioxide film has lower competency for a diffusion barrier against impurities, a leak of an impurity may occur out of an electrode. Furthermore, since this type of thin silicone dioxide film is formed by multiple atom layers, precise control is critical to mass-manufacture the films with high homogeneity.
Consequently, to ensure that further thinner elements with higher-speed processing performance are realized, “high-K material”, which provides the same higher level of field effect performance as that of the silicone dioxide even if the films made of them are thicker than the silicone dioxide film, have been proactively developed. Potential candidates for them include IV-group oxides such as zirconia and hafnia, III-group oxides such as alumina and yttria, and cilicates, which are solid solutions of silicone dioxide and any of these metals. IV-group and III-group oxides were used for gate insulating films of Si semiconductors at the early stage. However, after the fabrication technology for gate insulating films using silicone dioxide was established, because of its excellent properties, the silicone dioxide material has been exclusively used. Recently, the examples of semiconductors made of silicone dioxide have been reported; the field effect transistor, which uses zirconia for the gate insulating film, is described in IEDM'99 Tech. Digest pp.145, IEEE, 1999, the field effect transistor, which uses hafnia for the gate insulating film, is descried in 2000 Symposium on VLSI Technology Digest of Technical Papers, and the field effect transistor, which uses alumina for the gate insulating film, is described in IEDM'00 Tech. Digest pp.223, 2000. The method for fabricating metallosilicate is described in, for example, the Official Gazette of JP-A No. H11-135774.
Among them, the materials other than alumina cannot endure high-temperature heat treatment such as activating heat treatment because problems may occur including deterioration in withstand voltage due to a crystallized insulating film, reaction between the gate insulating film and the gate electrode, and a low-dielectric constant layer created on the interface of a Si substrate gate insulating film. Moreover, for the structure, in which a high-dielectric constant gate insulating film and a metal gate electrode are combined, such a problem occurs that the metal electrode has poor heat resistance. One of methods for solving the problem of deterioration due to high-temperature heat treatment is to use a replacement gate process. The replacement gate process is described in, for example, the U.S. Pat. No. 5,960,270. Especially, after a gate electrode pattern is formed in the same manner as a process for manufacturing an ordinary MOSFET, the gate pattern is used as a mask for self-coherent ion plantation of impurities and activating heat treatment to form a diffusion zone. This gate electrode is referred to as a dummy gate because it is peeled off later. By this method, after an interlayer dielectric is formed around the dummy gate, the dummy gate is peeled off to form a groove, a gate insulating film is deposited on the inner wall of the groove, and a metal material is embedded to form the gate electrode. The use of this method can drop the temperatures in the heat treatment process after gate electrode formation.
In addition, in the Official Gazette of JP-A No. 2001-15746″, the method for fabricating the semiconductor device is described, by which a double sidewall consisting of an oxide film and a nitride film is deposited on the sidewall of the dummy gate, the oxide film and the dummy gate insulting film are peeled off from the sidewall, and then a high-dielectric constant gate insulating film is deposited. Even if this method is used, finally the groove gets thick by the thickness of the oxide film on the sidewall.
As the micro-fabrication technology for transistors has advanced, a junction depth must be reduced to suppress the short channel effect. For example, when a gate length reaches 100−50 nm, the junction depth should be reduced to about 30 nm. Since the horizontal enlarged area of an extension is as large as 0.6-0.7 times the junction depth, the overlap between the gate electrode and a source drain is made small accordingly. However, as shown in
FIG. 23
, a problem may occur that an ON-state drain electric current (ON-current) suddenly decreases when the overlap is reduced to 20 nm or smaller. On the other hand, a too large overlap may cause such problems that since the area, to which a large electric field is applied, is enlarged in OFF state, an OFF current becomes large and the short channel effect is made more severe. To solve the problems, it is required that the junction depth and the overlap length be precisely controlled for micro transistors.
Besides, when the gate insulating film is deposited using the replacement gate process, the insulating film is deposited not only at the bottom but also on the sidewall of the groove. Accordingly, as shown in
FIG. 24
, the source/drain extension has an offset distance from the gate electrode equal to the thickness of the gate insulating film. If any high-k material is used for the gate insulating film, the ON-current is made small due to a decrease in overlap length because the thickness of the film is about 3-10 nm.
The conventional art described in the above-mentioned Official Gazette of JP-A No. 2001-15746 is intended to protect the sidewall covered with the cap nitride film when the sidewall oxide film and the cap nitride film are peeled off, and not to control the overlap between the source/drain extension and the gate electrode. This means that the conventional art has no technological concept, on which the overlap between the source/drain extension and the gate electrode is controlled. Therefore, in the conventional art, there is no technological concept cannot be found that the thickness of the sidewall oxide film and the thickness of the high-dielectric constant gate insulating film are made almost equal.
An object of the present invention is to provide a semiconductor device, which is a MISFET with a replacement gate electrode, ensuring a large ON-current.
Another objective of the present invention is to provide a method for manufacturing the semiconductor, which can regulate the overlap length of the ISFET with a replacement gate electrode to control a decrease in ON-current.
SUMMARY OF THE INVENTION
In order to achieve the above-mentioned objectives, the semiconductor of the present invention is so structured
Horiuchi Masatada
Onai Takahiro
Torii Kazuyoshi
Tsuchiya Ryuta
Chen Jack
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
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