Semiconductor device having a redundant memory cell and...

Details Semiconductor device having a redundant memory cell and... Semiconductor device having a redundant memory cell and...

2005-10-18

2005-10-18

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

06956778

ABSTRACT:
A semiconductor device includes a prime memory cell array, a redundant memory cell array, a holding circuit, a group of access lines, and first and second controlling circuits. The prime memory cell array includes prime memory cells. The redundant memory cell array includes redundant memory cells. The holding circuit holds an address of a defective memory cell. The access lines are respectively connected to the redundant memory cells. The first controlling circuit supplies a substitution command to substitute a redundant memory cell for the defective memory cell corresponding to the address held in the holding circuit, through the group of access lines to the defective memory cell. The second controlling circuit, when a plurality of portions of the holding circuit holds the address of the defective memory cell, disables all but one of the plurality of portions which hold the address of the defective memory cell.

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patent: 6501693 (2002-12-01), Takatsuka et al.
patent: 6597607 (2003-07-01), Koshita
patent: 5-54692 (1993-03-01), None

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