Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-11-07
2004-11-09
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06816419
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for recovering the same, and more particularly to a redundancy technique.
2. Description of the Related Art
In recent years, a redundancy technique is widely used in semiconductor devices, such as semiconductor memory devices in particular, in order to improve the manufacturing yield. The redundancy technique means a technique of adding redundant elements to prime elements (e.g., word lines, column lines or I/O lines). If one of the prime elements has a defect, the defective element is replaced with a redundant element, so that the defect can be remedied. The term “redundancy” originally means duplication or repetition of elements. However, as the technique for replacing a defective portion with a redundant line (or a redundant memory cell) is generalized, the replacement itself has come to be called “redundancy technique”. Therefore, in this specification, the term “redundancy” means “recovery of the semiconductor device including a defective portion by use of a redundant line or redundant memory cell”.
The conventional redundancy technique will be described with reference to
FIGS. 1A and 1B
.
FIGS. 1A and 1B
are schematic diagrams showing a word line redundancy system in a conventional DRAM (Dynamic Random Access Memory).
FIG. 1A
shows a case in which the word line has no defect, while
FIG. 1B
shows a case in which the word line has a defect.
When a row address and a word line select command are input to a row control circuit
100
from outside, a redundancy control circuit
200
compares the input row address with redundancy information. The redundancy information means the address of a defective word line. The redundancy information is stored in a fuse, a latch or the like during a memory test time. Access to the memory is performed so as to avoid a defective portion by virtue of the redundancy information.
If the redundancy information does not match with the row address, the redundancy control circuit
200
determines that replacement of the word line is unnecessary. Accordingly, a row decoder
300
selects a word line for normal access (prime word line) (see FIG.
1
A). If the redundancy information matches with the row address, the redundancy control circuit
200
determines that replacement of the word line is necessary. Accordingly, the row decoder
300
selects a redundant word line in place of the prime word line (see FIG.
1
B).
FIG. 2
is a block diagram of the redundancy control circuit
200
and the row decoder
300
.
The row decoder
300
has prime word line drivers
310
for the respective prime word lines, and redundant word line drivers
320
for the respective redundant word lines. Each of the prime word line drivers
310
activates the corresponding prime word line, and each of the redundant word line drivers
320
activates the corresponding redundant word line.
The redundancy control circuit
200
has redundancy information storing circuits
210
and a NOR gate
220
. Each of the storing circuits
210
is connected to the corresponding redundant word line and stores redundancy information. In the example shown in
FIG. 2
, the respective storing circuits
210
replace the prime word line
5
with the redundant word line
0
, the prime word line
26
with the redundant word line
1
, the prime word line
116
with the redundant word line
2
, and the prime word line
473
with the redundant word line
3
. Assume that, for example, the row address “
5
” is input. The row address is compared to all redundancy information. In the example shown in
FIG. 2
, the row address “
5
” matches with the redundancy information “
5
” corresponding to the redundant word line
0
. In this case, the output of the redundancy match line corresponding to the redundant word line
0
is set to “H” level. As a result, the redundant word line driver
320
activates the redundant word line
0
. The NOR gate
220
carries out the logical OR among the outputs of all redundancy match lines. The result of the logical OR operation is input to the prime word line drivers
310
through a prime word line non-select line NSL. In the example shown in
FIG. 2
, if the output of any redundancy match line is at “H” level, the prime word line non-select line NSL is set to “L” level. In this case, the prime word line drivers
310
do not activate the prime word lines. Therefore, only the cells connected to the redundant word lines can be accessed.
FIG. 3
is a circuit diagram showing a structure of the redundancy information storing circuit
210
. Although
FIG. 3
shows details of only the circuit corresponding to the redundant word line
0
, all of the circuits corresponding to the other redundant word lines have the same structure.
The redundancy information is held in a node al of a latch
211
in every bit. For example, in the case of a 9-bit row address, each of bits RA
0
to RA
8
is compared to the bit of the redundancy information held in each latch
211
by a comparing circuit
212
. If the row address matches with the redundancy information, the comparing circuit
212
outputs an “H” level signal. Information held in a latch
213
determines whether to use the redundancy information held in the redundancy information storing circuit
210
. For example, if the node b
1
of the latch is at the “H” level, the redundancy information is used. The latch outputs an “H” level signal. An AND gate
214
carries out the logical AND among the outputs of the comparing circuits
212
and the output of the latch
213
. The result of the logical AND operation is output to the redundancy match line. Thus, if all bits of the row address match with all bits of the redundancy information and the latch
213
holds the “H” level, the “H” level signal appears in the redundancy match line. Then, the redundant word line corresponding to the redundancy match line is selected. In this case, the output of the NOR gate
220
is at “L” level. Accordingly, the prime word line is in the non-select state as described above.
The conventional structure described above has the following problem: that is, even if a redundant word line is substituted for a prime word line, if the redundant word line has a defect, it is very difficult to recover the redundant word line.
FIG. 4
shows this state.
In the example shown in
FIG. 4
, a redundant word line r
0
is substituted for a prime word line p
5
having a defect. However, the redundant word line r
0
also has a defect. Since it is very difficult to recover the redundant word line r
0
, the chip including these lines is determined to be defective.
In the case described above, it is necessary to substitute another redundant word line for the defective redundant word line. This technique is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 5-54692, paragraphs [0013]-[0017], etc.
FIGS. 5A and 5B
are schematic diagrams of a redundancy system according to a first embodiment the invention disclosed in Jpn. Pat. Appln. KOKAI Publication No. 5-54692. According to this system, each of resubstitution circuits
405
a
and
405
b
must have two fuses in order to re-substitute a redundant word line. Therefore, the system has the drawback that the chip has a large area.
Further, Jpn. Pat. Appln. KOKAI Publication No. 5-54692, paragraphs [0018]-[0022], describes a second embodiment, in which no fuse for re-substitution is used.
FIG. 6A
is a schematic diagram of a redundancy system according to the second embodiment described in Jpn. Pat. Appln. KOKAI Publication No. 5-54692.
According to this system, a spare select line decoder receives an input signal/SDE from an adjacent spare select line decoder. It does not operate if the input signal/SDE is at “H” level. Therefore, selection of both spare select lines L
5
and L
6
can be prevented. In this system, the signal/SDE is always input to the adjacent spare select line decoder. The substitution is carried out as shown in FIG.
6
B. First, when “one”
Frommer & Lawrence & Haug LLP
Kabushiki Kaisha Toshiba
Phung Anh
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