Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2001-10-04
2003-10-21
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S112000, C326S119000, C326S034000
Reexamination Certificate
active
06636078
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a semiconductor device and more particularly to a semiconductor device having circuitry using insulated gate field effect transistors (IGFETs) and improving leakage current through such devices.
BACKGROUND OF THE INVENTION
As sizes on devices such as metal oxide semiconductor field effect transistors (MOSFETs) have become smaller, device isolation techniques, such as conventional LOCOS (local oxidation of silicon), have been replaced with a STI (shallow trench isolation) method.
In FIG.
8
(
a
), a top plan view of the layout of a conventional MOSFET is set forth. In FIG.
8
(
b
), a cross-sectional view along the line A—A of conventional MOSFET is set forth.
Referring now to FIG.
8
(
a
), the conventional MOSFET includes an active area ACT. The active area ACT defines the region in which the conventional MOSFET is to be confined. A polysilicon wiring POL crosses the active area to form a gate electrode GG. Impurities are implanted and diffused into the active area ACT on both sides of the polysilicon wiring POL to form a drain region DD and source region SS. STI is formed in an area surrounding the active area ACT in order to isolate the conventional MOSFET from other device elements. The STI is not illustrated in FIG.
8
(
a
).
Referring now to FIG.
8
(
b
), a cross sectional view along the line A—A of the conventional MOSFET of FIG.
8
(
a
) is set forth.
As illustrated in FIG.
8
(
b
), a gate oxide film GOX is formed as a gate isolation film on the semiconductor substrate SUB over the active area ACT. Polysilicon wiring POL forming the gate electrode GG is formed on top of the gate oxide film GOX across the active area ACT. Although not illustrated in FIG.
8
(
b
), the drain and source regions are formed on both sides of the gate GG in the active area ACT. A trench is formed around the active area ACT and silicon oxide SOX is formed within the trench to form the STI structure.
As device structures continue to become smaller due to miniaturization, the gate width as well as the thickness of the gate oxide film GOX and gate length are reduced. In the case of a conventional MOSFET, which uses LOCOS as the isolation structure, the threshold voltage tends to rise due to a narrow channel effect when a gate width is reduced. On the other hand, in the case of a conventional MOSFET, which uses STI as the isolation structure, the threshold voltage tends to decrease near the boundary between the active area ACT and the STI (field area). This threshold voltage fluctuation will be described with reference to FIG.
9
.
Referring now to
FIG. 9
, a cross-sectional view of a region of the conventional MOSFET illustrated in
FIG. 8
is set forth. The region illustrated in
FIG. 9
, is the portion indicated by general reference character K in FIG.
8
and is a portion including a boundary between the active area ACT and the STI. The cross-sectional view of
FIG. 9
, illustrates a n-type MOSFET.
As illustrated in
FIG. 9
, the STI is the vertically formed silicon oxide SOX. In the case of a n-type MOSFET a p-type impurity such as boron (illustrated by B) is included in the substrate. At the interface region between the active area ACT and the silicon oxide SOX, boron B can out-diffuse and become trapped in the silicon oxide SOX. As a result, the impurity density is reduced around the boundary between the active area ACT and the STI. This causes the threshold voltage of the MOSFET to decrease in this area and can create an increase leakage current in this region.
Also, a ridge T in silicon oxide can be formed at the interface between the gate oxide GOX and silicon oxide SOX formed in the STI. The ridge T can cause an increased electric field produced in the region around the boundary of active area ACT and STI.
Thus, in the threshold voltage tends to be lower in the region near the boundary of the active region ACT and the STI structure. Also, the electric field in this region may be increased due to a ridge T produced in the silicon oxide. These effects can cause an increase in sub-threshold currents in this area, which increases power consumption.
On the other hand, when a LOCOS structure is used for device isolation, the field oxide region next to the active area ACT may be an arc or bird beak type structure. Thus, with the lower surface area at the interface, a smaller amount of impurities may out-diffuse from the channel area to the field area and the leakage current may not be increased to the same degree.
However, as disclosed in Japanese Patent Application Laid-Open 9-321277, it is pointed out that the threshold voltage tends to decrease when the LOCOS structure is used as well as when the STI structure is used.
Thus, in a conventional MOSFET, it is known that leakage current can be increased around the boundary between the active area ACT and a field area (such as STI or LOCOS). This is particularly the case when the gate width is reduced. To suppress the leakage current, methods have been disclosed in Japanese Patent Application Laid-Open No. 9-321277 and Japanese Patent Application Laid Open no. 2000-82808. The approach disclosed in Japanese Patent Application Laid-Open No. 9-321277 uses a leveled profile in the depth direction of a threshold voltage control layer. The approach disclosed in Japanese Patent Application Laid-Open No. 2000-82808 uses a barrier layer to suppress the out-diffusion of impurities.
However, in the above-mentioned conventional approaches, the method of suppressing the leakage current due to the decrease in gate width is accomplished by modifying the device structure. The modification of the device structure may be difficult from a process view-point and may not be effective due to non-ideal process results. This is particularly the case when used in a circuit that is manufactured in large quantities. Thus it can be difficult to effectively suppress the leakage current with these approaches. Also, when these methods are used, the average threshold voltage in a device may increase. This can lower the current driving ability of the MOSFET. In this way, the circuit operating speed is reduced.
Referring now to
FIG. 10
, a circuit schematic diagram of a conventional predecoder is set forth. The conventional predecoder is used to select a word line formed in a memory cell array in a semiconductor memory device. The conventional predecoder illustrated in
FIG. 10
, can be illustrative of a circuit in which sub-threshold leakage can cause undesired current consumption. The sub-threshold current leakage can be greatly magnified by the fact that such a conventional predecoder may be repeated a large number of times on a typical semiconductor memory device.
The conventional predecoder of
FIG. 10
includes NAND gate circuits (GJ
1
to GJ
4
). NAND gate circuits (GJ
1
to GJ
4
) commonly receive address signal A and respectively receive activating address signals (B
1
to B
4
). Address signal A is used to collectively select NAND gate circuits (GJ
1
to GJ
4
) and address signals (B
1
to B
4
) are used to individually select one of NAND gate circuits (GJ
1
to GJ
4
). NAND gate circuits (GJ
1
to GJ
4
) respectively produce output signals (D
1
to D
4
).
Each NAND gate circuit (GJ
1
to GJ
4
) has p-type MOSFETs (PJ
1
and PJ
2
) and n-type MOSFETs (NJ
1
and NJ
2
). P-type MOSFET PJ
1
has a source connected to a power supply, a drain connected to the respective output node (D
1
to D
4
) and a gate connected to address signal A. P-type MOSFET PJ
2
has a source connected to a power supply, a drain connected to the respective output node (D
1
to D
4
) and a gate connected to the respective address signal (B
1
to B
4
). N-type MOSFET NJ
1
has a source connected to a drain of n-type MOSFET NJ
2
, a drain connected to the respective output node (D
1
to D
4
) and a gate connected to address signal A. N-type MOSFET NJ
2
has a source connected to ground and a gate connected to the respective address signal (B
1
to B
4
).
In the conventional predecoder, only one of NAND gate circuits (GJ
1
to GJ
4
) is
Chang Daniel
NEC Electronics Corporation
Sako Bradley T.
Walker Darryl G.
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