Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified encapsulant
Reexamination Certificate
2002-08-05
2004-10-12
Parekh, Nitin (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With specified encapsulant
C257S787000, C257S690000, C257S675000, C257S666000, C257S706000, C257S707000, C257S712000, C257S713000, C257S692000, C257S782000, C257S783000
Reexamination Certificate
active
06803667
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based on Japanese Patent Application No. 2001-242077 filed on Aug. 9, 2001 the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising a semiconductor element and a metal block, e.g., a heat sink, which is bonded to electrode surfaces of the semiconductor element through an electrically conductive bonding material.
2. Description of Related Art
For example, a semiconductor chip (semiconductor element) in a power semiconductor device (e.g., IGBT, MOSFET, or a power IC including them) for a high withstand voltage and a high current generates a great deal of heat while it is in use. Therefore, the semiconductor chip is required to have a construction for improving its heat radiating property. For example, a heat sink is useful for meeting this requirement. The heat sink can be bonded to the semiconductor chip through a solder layer.
Since such a semiconductor device is used in a wide temperature range, it is necessary to prevent its failure induced by thermal stress.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device which can prevent a large deformation of a protective film even when subjected to a large thermal stress, thereby making it possible to diminish short-circuit of an electrode layer.
Having conducted trial manufacture and experiments, the inventors in the present case found out a condition capable of preventing a large deformation of an organic type protective film and thereby capable of diminishing a short-circuit defect of an electrode layer when a large thermal stress is applied to the semiconductor device of the above construction. This condition is expressed as t
1
<t
2
wherein t
1
stands for the thickness of the electrode layer, here the electrode layer covered with the protective film, and t
2
stands for a substantial thickness of the protective film. Under this thickness condition, even if the protective film is deformed by a thermal stress, it is possible to prevent a shoulder portion of the electrode layer from breaking the protective film and being exposed.
We have confirmed that the protective film preferably has an elastic modulus at room temperature of 1.0-5.0 GPa and a thermal expansion coefficient of 35-65×10
−6
/° C.
It is preferable that the elastic modulus of the protective film be smaller than that of the bonding material so as to absorb strains induced by a thermal expansion of the electrically conductive material and that of the semiconductor chip. Further, in order to prevent an excessive deformation of the protective film it is preferable that the thermal expansion coefficient of the protective film be almost equal to that of the bonding material. For example, in case of using an Sn-based solder as the bonding material, its thermal expansion coefficient is 30×10
−6
/° C. or so and it is desirable to select one having a thermal expansion coefficient in the range of 35-65×10
−6
/° C. as noted above.
By thus selecting appropriate elastic modulus and thermal expansion coefficient of the protective film, even if a large thermal stress is applied thereto, the protective film can withstand the thermal stress and is prevented from being largely deformed. As a result, a short-circuit defect of the electrode layer can be diminished.
If an Sn-based solder is used as the bonding material, and given that a thermal expansion coefficient of a metal block (heat sink) on the surface side of the semiconductor element is &agr;
1
, that of the semiconductor element is &agr;
2
, the chip size of the semiconductor element is a×b, and a temperature difference between highest and lowest temperatures in a working environment is &Dgr;T, it is desirable to construct the semiconductor device so that the following relationship is established:
t
1
<
t
2
≤
1
2
×
a
2
+
b
2
×
&LeftBracketingBar;
α1
-
α2
&RightBracketingBar;
×
Δ
T
Further, in the case of a construction wherein a metal block (heat sink) is disposed also on the back side of the semiconductor element, and given that an apparent thermal expansion coefficient of a composite system comprising the surface-side metal block (heat sink) of the semiconductor element and solder is &agr;
1
e
, that of a composite system comprising the back-side metal block (heat sink) and the semiconductor element is &agr;
2
e
, the chip size of the semiconductor element is a×b, and a temperature difference between highest and lowest temperatures in the working environment is &Dgr;T, it is desirable to construct the semiconductor device so that the following relationship is established:
1
2
×
a
2
+
b
2
×
&LeftBracketingBar;
α1
e
-
α2
e
&RightBracketingBar;
×
Δ
T
≤
t
2
Through trial manufacture and experiments we have confirmed that even if a large thermal stress is induced due to a difference in thermal expansion coefficient between the semiconductor element and the metal block (heat sink), it is possible to diminish a short-circuit defect of the electrode layer if a surface asperity of the ground for the bonding material which bonds the metal block to the semiconductor element is flat or is concave above the electrode layer.
REFERENCES:
patent: 5757081 (1998-05-01), Chang et al.
patent: 6028348 (2000-02-01), Hill
patent: 6486563 (2002-11-01), Lin
U.S. patent application Ser. No. 10/201,556, Hirano et al., filed Jul. 24, 2002.
U.S. patent application Ser. No. 09/717,227, Mamitsu, filed Nov. 22, 2000.
U.S. patent application Ser. No. 10/127,613, Teshima, filed Apr. 25, 2002.
U.S. patent application Ser. No. 10/321,365, Teshima et al., filed Dec. 18, 2002.
Hirano Naohiko
Mamitsu Kuniaki
Okura Yasushi
Denso Corporation
Parekh Nitin
Posz & Bethards, PLC
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