Semiconductor device having a plurality of output signals

Details Semiconductor device having a plurality of output signals Semiconductor device having a plurality of output signals

2002-03-28

2004-02-17

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S194000, C365S230050, C365S230080, C365S226000, C365S227000, C327S108000

Reexamination Certificate

active

06693842

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, to a semiconductor device having a plurality of output signals.
2. Description of the Related Art
A semiconductor memory device stores data, and the stored data is output in response to a predetermined signal. As the memory capacity of semiconductor memory devices increase, the amount of data that is input and output also increases.
FIG. 1
is a circuit diagram of an output portion of a conventional semiconductor memory device having a plurality of output signals. An output portion
111
includes a plurality of output drivers DR
1
through DRn. The output drivers DR
1
through DRn buffer signals DI
1
through DIn output from within a semiconductor memory device and output signals DQ
1
through DQn. The output signals DQ
1
through DQn are transmitted outside the semiconductor memory device. Each of the output drivers DR
1
through DRn generally has both an NMOS transistor and a PMOS transistor. The NMOS transistors and the PMOS transistors switch the signals DI
1
through DIn from logic “low” to logic “high” or from logic “high” to logic “low”. A large amount of current flows from an output node of the output portion
111
to a power line
121
or a ground line
131
during the switching operation if the input signals DI
1
through Din are input into the output portion
111
at the same time. Here, switching noise is present in the output signals DQ
1
through DQn due to parasitic inductance components existing in the power line
121
or the ground line
131
. As a result, the output signals DQ
1
through DQn are delayed or distorted. The switching noise increases in proportion to the amount of current per time. In other words, the greater current, the greater the switching noise.
The switching noise does not matter much if a small number of signals are output from the output portion
111
at the same time. However, if a large number of signals are output from the output portion
111
at the same time, in particular, if the number of output signals switched in one direction is not equal to the number of output signals switched in an opposite direction, skewing of the output signals occurs due to simultaneous switching noise. The reason is that gate voltages of the NMOS transistors and the PMOS transistors change due to fluctuations in power voltage or ground voltage. Skewing of the output signals increases when the number of output signals DQ
1
through DQn of the semiconductor memory device increases, the number of parasitic inductance components increases, and when the semiconductor memory device is in a high-speed operation.
FIGS. 2A
,
2
B, and
2
C are diagrams illustrating waveforms of 16 signals output at the same time from the output portion
111
shown in FIG.
1
.
FIG. 2A
illustrates the waveform diagrams of the output signals DQ
1
through DQ
16
when the number of output signals (that is output signals DQ
1
through DQ
8
) that simultaneously changed from logic “high” to logic “low” is the same as the number of output signals (i.e., output signals DQ
9
through DQ
16
) that simultaneously changed from logic “low” to logic “high”. As described, simultaneous switching noise occurs in the output signals DQ
1
through DQ
16
if the number of output signals (i.e., output signals DQ
1
through DQ
8
) that simultaneously changed from logic “high” to logic “low” is the same as the number of output signals (i.e., output signals DQ
9
through DQ
16
) that simultaneously changed from logic “low” to logic “high”. Thus, skewing of the output signals DQ
1
through DQ
16
does not occur.
However, as shown in
FIG. 2B
, skewing t
1
occurs when output signals DQ
1
through DQ
15
are simultaneously changed from logic “high” to logic “low” and output signal DQ
16
is changed from logic “low” to logic “high”. Alternatively, as shown in
FIG. 2C
, when the output signals DQ
1
through DQ
15
are simultaneously changed from logic “low” to logic “high” and the output signal DQ
16
is changed from logic “high” to logic “low”, skewing t
2
occurs.
SUMMARY OF THE INVENTION
To solve the above and other related problems of the prior art, there is provided a semiconductor device that reduces the skewing of signals occurring when a plurality of signals are simultaneously output.
According to an aspect of the present invention, there is provided a semiconductor device including a first pre-driver, a second pre-driver, and an output portion. The first pre-driver operates in response to a first signal. The second pre-driver operates in response to a second signal. The output portion outputs an output signal external to the semiconductor device in response to signals output from the first and second pre-drivers. A first ground line supplies a first ground voltage to the output portion and the first pre-driver and a first power line supplies a first power voltage to the output portion and the second pre-driver.
According to another aspect of the present invention, the semiconductor device further comprises a second power line for supplying a second power voltage. The first pre-driver is supplied with any one of the first power voltage or the second power voltage via the first power line or the second power line, respectively. The first power voltage being different from the second power voltage.
According to yet another aspect of the present invention, the semiconductor device further comprises a second ground line for supplying a second ground voltage. The second pre-driver is supplied with any one of the first ground voltage or the second ground voltage via the first ground line or the second ground line, respectively. The first ground voltage being different from the second ground voltage.
According to yet still another aspect of the present invention, the output portion comprises a PMOS transistor gated by a signal output from the first pre-driver for transmitting the second power voltage to an output node. A PMOS transistor is gated by a signal output from the second pre-driver for transmitting the second ground voltage to the output node. The output signal of the output portion is output from the output node.
According to yet still further another aspect of the present invention, the semiconductor device further includes a decoupling capacitor connected between the first power line and the first ground line to maintain a uniform range of fluctuations in the first power voltage and the first ground voltage during the switching of the output portion.
According to a further aspect of the present invention, there is provided a semiconductor device having a plurality of output portions. Each of the plurality of output portions includes a plurality of PMOS transistors, a plurality of first buffers, a plurality of NMOS transistors, and a plurality of second buffers. Each of the plurality of PMOS transistors has a gate, a drain, and a source. The drain of each of the plurality of PMOS transistors is connected to a predetermined node, and the source of each of the plurality of PMOS transistors is supplied with a first power voltage. Each of the plurality of first buffers being connected to the gate of each of the plurality of PMOS transistors. Each of the plurality of NMOS transistors has a gate, a drain, and a source. The drain of each of the plurality of NMOS transistors is connected to the predetermined node, and the source of each of the plurality of NMOS transistors is supplied with a first ground voltage. Each of the plurality of second buffers is connected to the gate of each of the plurality of NMOS transistors. The plurality of first buffers are supplied with the first ground voltage, the plurality of second buffers are supplied with the first power voltage, and a signal output from a previous portion of the semiconductor device is input into the first and second buffers at predetermined time intervals.
According to a yet further aspect of the present invention, each of the first buffers have a ground terminal connected to a line transmitting the f

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