Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2005-01-26
2008-08-26
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S622000, C438S624000, C438S625000, C438S626000, C438S631000, C438S645000, C438S697000, C438S760000
Reexamination Certificate
active
07416985
ABSTRACT:
A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall surface and a bottom surface covered with a first barrier metal film, a via-hole formed in the second interlayer insulation film and having a sidewall surface and a bottom surface covered with a second barrier metal film, an interconnection pattern filling the interconnection trench, and a via-plug filling the via-hole, wherein the via-plug makes a contact with a surface of the interconnection pattern, the interconnection pattern has projections and depressions on the surface, the interconnection pattern containing therein oxygen atoms along a crystal grain boundary extending from the surface toward an interior of the interconnection pattern with a concentration higher than a concentration at the surface.
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Masaaki Hatano et al.,EM lifetime improvement of Cu damascene interconnects by P-SiC cap layer, IITC—09—18 (2002).
Horiuchi Hiroshi
Kitada Hideki
Miyajima Motoshu
Watani Hirofumi
Yamamoto Tamotsu
Fujitsu Limited
Jr. Carl Whitehead
Mitchell James M
Westerman, Hattori, Daniels & Adrian , LLP.
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