Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-09-15
2002-09-10
Graybill, David E. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S759000, C257S760000, C257S503000, C257S508000, C257S763000, C257S764000, C257S775000, C438S624000, C438S625000, C438S774000, C438S622000, C438S637000
Reexamination Certificate
active
06448651
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a multi-level metallization without a contact pad that allows large scale integration and a fabricating method thereof.
2. Discussion of Related Art
In the era of deep sub-micron, the integration rate of semiconductor devices grows higher in inverse proportion to their size. As the size of a conductive plug for connecting between devices and the space and width between metallization layers also become smaller, it is necessary to apply a multi-level metallization, W-plug, Al-reflow, and chemical mechanical polishing (CMP) processes to all semiconductor fabrications.
FIGS. 1
a
to
1
e
illustrates the process of fabricating a conventional semiconductor device having a multi-level metallization. As shown in
FIG. 1
a
, a field oxide layer
12
is first formed on a device isolation region on a semiconductor substrate
10
. The field oxide layer
12
defines an active area for an active device. Impurities are implanted into the substrate
10
. The impurities diffuse forming an active area
14
in the substrate
10
. A first insulating layer
16
is formed on the substrate
10
including the field oxide layer
12
and selectively etched to thereby expose a predetermined surface of the active area
14
. The first and second contact hole h
1
and h
2
, respectively, are formed on the etched part of the active area
14
.
Referring to
FIG. 1
b
, a conductive layer
18
on the first insulating layer
16
is formed.
Referring to
FIG. 1
c
, the conductive layer
18
is subjected to a CMP or etch-back process until the surface of the first insulating layer
16
is exposed. The first and second conductive plugs
18
a
and
18
b
are formed in the first and second contact holes h
1
and h
2
, respectively. A conductive layer is formed on the first insulating layer
16
including the conductive plugs
18
a
and
18
b
. The conductive layer is selectively etched to expose a predetermined surface of the first insulating layer
16
such that a first conductive layer pattern
20
connected to the first conductive plug
18
a
, a contact pad
22
connected to the second conductive plug
18
b
, and a second conductive layer pattern
24
are formed simultaneously. At this time, the first conductive pattern
20
connects the two upper/lower conductive plugs as well as serving as an electric metallization layer. The contact pad
22
connects the two upper/lower conductive plugs. The second conductive pattern
24
serves as an electric metallization wire.
The first conductive pattern
20
, contact pad
22
, and second conductive pattern
24
are spaced at a distance E preventing a short from developing between the patterns
20
and
24
and the pad
22
. The spacer E is generally greater than about 0.4 &mgr;m. The length of the spacer E depends on the resolution of the exposure equipment and the etching ability of the conductive layer consisting of the first and second conductive patterns
20
and
24
and contact pad
22
.
Referring to
FIG. 1
d
, a second insulating layer
26
is formed on the first insulating layer
16
and the first and second conductive layers
20
and
24
and contact pad
22
. The second insulating layer
26
is selectively etched thereby exposing a predetermined surface of the first conductive layer
20
and contact pad
22
. A third and fourth contact holes h
3
and h
4
, respectively, are formed in the insulating layer
26
.
The contact pad
22
is normally formed to be wider than the fourth contact hole h
4
. This is because light exposure during the photolithography process that forms the fourth contact hole h
4
misaligns the fourth contact hole h
4
to the contact pad
22
. Thus, an inferior contact can occur between the contact pad
22
and the subsequently formed fourth conductive plug. To prevent this type of interior contact from forming, the contact pad
22
is currently fabricated with an overlap margin labeled as C in
FIG. 1
d.
Referring to
FIG. 1
e
, the third and fourth conductive plugs
28
a
and
28
b
are formed in the third and fourth contact holes h
3
and h
4
, respectively, using the same method as described for forming the first and second contact holes h
1
and h
2
, respectively. A third conductive pattern
30
connected to the third conductive plug
28
a
and the fourth conductive pattern
32
connected to the fourth conductive plug
28
b
are formed simultaneously by selectively etching a conductive layer deposited on the surface of the second insulating layer. The third and fourth conductive pattern,
30
and
32
, respectively, serve as an electric metallization wire.
To summarize, the first insulating layer is formed on the semiconductor substrate
10
having the active area
14
. The first and second contact holes h
1
and h
2
are formed on and passing through the first insulating layer
16
thereby exposing a predetermined surface of the active area
14
. The first and second conductive plugs
18
a
and
18
b
are formed in the first and second contact holes h
1
and h
2
, respectively. The contact pad
22
is connected to the second conductive plug
18
b
and interposed between the first conductive pattern
20
, and the second conductive pattern
24
. Each of the first and second conductive patterns
20
and
24
, respectively, are spaced predetermined distance apart. The second insulating layer
26
is formed on the first insulating layer
16
. The third and fourth contact holes h
3
and h
4
are formed passing through the second insulating layer
26
to thereby expose a predetermined surface of the first conductive pattern
20
and contact pad
22
. The third and fourth conductive plugs
28
a
and
28
b
are formed in the third and fourth contact holes h
3
and h
4
, respectively. The third conductive pattern
30
is connected to the third conductive plug
28
a
and the fourth conductive pattern
32
is connected to the fourth conductive plug
28
b
. The third and fourth conductive patterns
30
and
32
are spaced a predetermined distance apart.
Assuming that the horizontal width of the fourth conductive plug
28
b
is A, and the spacer between the first and second conductive patterns
20
and
24
and contact pad
22
is E, the horizontal and vertical width of the contact pad is A+(2*C) and the fourth contact hole h
4
maintains a space greater than (C+E) to the first conductive pattern
20
. In addition, the horizontal length between the first and second conductive patterns
20
and
24
on the same line is A+(2*C)+(2*E).
FIG. 2
is a top view of the layout structure of the conventional semiconductor device shown in
FIG. 1
e
. Only the layout structure under the third and fourth conductive patterns
30
and
32
, respectively, directly associated with the invention is shown in FIG.
2
.
Referring to
FIG. 2
, the first conductive pattern
20
, contact pad
22
, and second conductive pattern
24
are spaced at a predetermined distance on the same line, having the contact pad
22
interposed. The second and fourth conductive plugs
18
b
and
28
b
are laid on/under the contact pad
22
, and are connected to each other.
The following problems may occur when a semiconductor device is manufactured using the process described above. When forming the contact pad
22
to electrically connect the second conductive plug
18
b
and the fourth conductive plug
28
b
, the size of the contact pad
22
is structured to include the overlap margin C to prevent misalignment. The size of the overlap margin makes it impossible to reduce the width of the contact pad
22
not to exceed A+(2*C). The horizontal distance between the first and second conductive patterns
20
and
24
is actually larger than A+(2*C)+(2*E).
Limiting reduction of the pattern size in the horizontal direction in the semiconductor device makes large-scale integration of the device difficult if not impossible. Therefore, more effort is necessary to solve this problem. Accordingly, a
Graybill David E.
Marger & Johnson & McCollom, P.C.
Mitchell James
Samsung Electronics Co,. Ltd.
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