Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-10-15
2003-07-22
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S455000, C438S675000, C438S692000
Reexamination Certificate
active
06596622
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing it, and particularly to a semiconductor device having a multilayer pad formed by using tungsten CMP and a method of manufacturing it.
2. Background Art
A method of manufacturing a semiconductor device having a conventional multilayer pad structure will be explained with reference to FIG.
8
.
FIGS. 8
a
through
8
e
are respectively schematic cross-sectional views showing a semiconductor device in respective process steps of the conventional manufacturing method of the semiconductor device. Incidentally, the same drawings respectively show via holes in addition to pad portions.
As shown in
FIG. 8
a
, a lower barrier metal layer is first formed over a base substrate
1
with an interlayer film laminated over an Si substrate by a sputtering method. Further, a first Al layer is formed over the lower barrier metal layer by the sputtering method. Thereafter, RIE etching is carried out. Consequently, a first pad
2
a
, a first wiring
2
b
and lower barrier metal layers
11
a
and
11
b
corresponding to them are formed.
Next, as shown in the same
FIG. 8
b
, an oxide film layer
3
used as an insulating film layer is formed over the first pad
2
a
and the first wiring
2
b
, followed by execution of photoengraving and RIE etching. Thus, a plurality of openings
4
c
defined so as to partly open the surface of the first pad
2
a
, and a via hole
4
b
defined so as to partly open the surface of the first wiring
2
b
are formed. Here, the plurality of openings
4
c
and a plurality of oxide film layers
3
a
are formed over the surface of the first pad
2
a
. The open area of each opening
4
c
is approximately equal to that of the via hole
4
b.
Next, as shown in the same
FIG. 8
c
, a first barrier metal layer
5
is formed over the oxide film layer
3
by the sputtering method. A tungsten layer
6
used as a plug layer is formed over the first barrier metal layer
5
by a CVD method. Here, the first barrier metal layer
5
is laminated along hole shapes of the plurality of openings
4
c
and the via hole
4
b
, and the surface thereof is brought into concavo-convex forms. On the other hand, the tungsten layer
6
is laminated without extending along the hole shapes of the plurality of openings
4
c
and the via hole
4
b
, and the surface thereof is brought into planar form.
Next, the tungsten layers
6
a
and
6
b
and the first barrier metal layers
5
a
and
5
b
in the plurality of openings
4
c
and the via hole
4
b
are left behind as shown in the same
FIG. 8
d
. Further, other tungsten layer
6
, first barrier metal layer
5
and parts of oxide film layer
3
are removed by tungsten CMP. Afterwards, HF processing is done to prevent metal contamination.
Finally, as shown in the same
FIG. 8
e
, a second barrier metal layer and a second Al layer are sequentially formed over the oxide film layer
3
by the sputtering method. Further, desired second barrier metal layers
8
a
and
8
b
, second pad
9
a
and second wiring
9
b
are formed by RIE etching. Furthermore, a P-SiN layer
10
is formed over the second pad
9
a
and the second wiring
9
b
by the CVD method. An opening
12
is defined in the P-SiN layer
10
so as to open the surface of the second pad
9
a.
In the semiconductor device manufactured in the above-described process steps, wires and the like are thereafter bonded onto the surface of the second pad
9
a
through the opening
12
.
In the semiconductor device manufactured by the aforementioned conventional manufacturing method, cracks were produced in the oxide film layers
3
a
below the second pad
9
a
when the wire bonding was effected on the surface of the second pad
9
a
through the opening
12
. Namely, an external force (distributed load) corresponding to the bonding is instantaneously applied to the surface of the second pad
9
a
. While the second pad
9
a
is formed of Al having shock absorbency, it cannot accommodate its impactive force because its thickness is extremely thin. Therefore, the impactive force is applied even to the surfaces of the oxide film layers
3
a
and tungsten layers
6
a
placed below the second pad
9
a
. Since the oxide film layers
3
a
formed of SiO
2
or the like are low in ultimate strength as compared with the tungsten layers
6
a
, the cracks are produced in the oxide film layers
3
a
. Thus, when the cracks occur in the oxide film layers
3
a
, a secondary problem arises in that interlayer withstand pressure and reliability for temperatures are deteriorated.
In order to solve the aforementioned problems, only the tungsten layers
6
a
are considered to be formed between the first pad
2
a
and the second pad
9
a
without forming the oxide film layers
3
a
. In such a case, however, there is the fear of the occurrence of erosion in the first pad
2
a
by CMP.
Namely, the formation of only the tungsten layers
6
a
over the first pad
2
a
needs to form openings large in open area over the first pad
2
a
in advance, thereafter form tungsten layers and leave the tungsten layers only in the opening by CMP.
However, the tungsten layers each formed in the opening large in open area are polished in concave form by CMP. Namely, since a polishing rate per unit time with respect to tungsten is larger than a polishing rate per unit time with respect to a barrier metal, the tungsten layers formed in the openings placed in positions lower than the barrier metal layers would also be polished when the polishing of the barrier metal layers are brought to completion. Thus, the tungsten layers formed in the openings are polished in concave form. When the degree thereof increases, the polishing reaches up to the first pad, so-called erosion occurs.
Further, there is fear that when the erosion occurs in this way, the following two secondary problems will arise. One of the problems is that due to post-CMP HF processing (isotropic etching), the first pad corrodes, and a hollow portion is defined in the first pad, whereby reliability for temperatures is deteriorated. Another problem is that an external force produced by the aforementioned bonding, and an external force developed by contact of a test pin used upon a wafer inspection are applied to the first pad to thereby produce cracks in the base substrate below the first pad made thinly by polishing, whereby interlayer withstand pressure and reliability for temperatures are deteriorated.
SUMMARY OF THE INVENTION
The present invention has been made to solve the aforementioned problems. Therefore, the present invention aims to provide a semiconductor device which produces no cracks in an oxide film layer and a base substrate or the like even if an external force is applied to a pad portion, and which is free of the occurrence of erosion by tungsten CMP, and a manufacturing method thereof.
According to one aspect of the present invention, in a method of manufacturing a semiconductor device, a first pad is formed over a base substrate. An insulating film layer is formed over the first pad and thereafter a concave pad opening is defined in the insulating film layer so as to expose nearly the whole area of the surface of the first pad. A first barrier metal layer is formed over the first pad and the insulating film layer so as to extend along the concave shape of the pad opening. A plug layer is formed over the first barrier metal layer. The plug layer and the first barrier metal layer are CMP-polished to thereby expose the insulating film layer and leave the plug layer in the pad opening. A second barrier metal layer is formed over the plug layer. A second pad is formed over the second barrier metal layer.
Other and further objects, features and advantages of the invention will appear more fully from the following description.
REFERENCES:
patent: 5767005 (1998-06-01), Doan et al.
patent: 5903054 (1999-05-01), Sardella
patent: 5948698 (1999-09-01), Inohara et al.
patent: 5981378 (1999-11-01), Bothra
patent: 6011311 (2000-01-01), Hsing et al.
Chaudhuri Olik
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Toledo Fernando
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