Semiconductor device having a multi-layer interconnect structure

Details Semiconductor device having a multi-layer interconnect structure Semiconductor device having a multi-layer interconnect structure

1991-04-12

1992-09-15

Hille, Rolf

357 51, 357 53, 357 68, H01L 2348, H01L 2946, H01L 2954, H01L 2962

Patent

active

051482630

ABSTRACT:
A semiconductor device has a multi-layer structure comprising three or more interconnect layers formed over a substrate, one of these interconnect layers being a first power supply line and another metal interconnect layer being a second power supply line, the first and second power supply lines being arranged in a multi-level fashion such that one is superposed relative to the other in a plan view. That is, the power supply lines are arranged as a multi-layer metal interconnect layer array such that the first and second power supply lines are superposed in a multi-level fashion in a plan view.

REFERENCES:
patent: 4893170 (1990-01-01), Tokuda et al.
"Semiconductor Integrated Circuit Device ", Patent Abstracts of Japan, vol. 10, No. 205 (E-420) (2261) Jul. 17, 1986, & JP-A-61 046050 (NEC IC Microcomput Syst Ltd) Mar. 6, 1986.
Patent Abstracts of Japan, vol. 11 No. 59 (E-482) (2506) Feb. 24, 1987, & JP-A-61 218155, Sep. 27, 1986.

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