Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-16
2004-05-11
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S298000, C257S300000, C257S303000, C257S048000, C257S304000
Reexamination Certificate
active
06734481
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication process therefor, and more particularly, to a semiconductor device having a monitor pattern for measuring a characteristic of a transistor for a memory cell included in the memory cell of a DRAM (Dynamic Random Access Memory) and to a fabrication process therefor.
2. Description of the Background Art
First of all, description will be given of a semiconductor device having a prior art monitor pattern.
FIG. 48
is a plan view showing a configuration of a semiconductor device having a prior art monitor pattern.
FIGS. 49
,
50
,
51
and
52
are schematic sectional views taken on respective lines IL—IL, L—L, LI—LI and LII—LII of FIG.
48
.
Referring mainly to
FIG. 48
, in a monitor area, similar to a memory cell area, there are arranged plural conductive layers
105
corresponding to word lines and plural conductive layers
111
and
111
a
corresponding to bit lines such that any one of the former and any one of the latter intersect orthogonally with each other. Monitor transistors MT are located in the vicinity of respective corresponding intersections of plural conductive layers
105
and plural conductive layers
111
and
111
a.
Each of monitor transistors MT has a configuration equivalent to a transistor constituting a memory cell (hereinafter referred to as a memory cell transistor).
Referring to
FIGS. 48
to
52
, a monitor transistor MT is formed on a surface of a silicon substrate
101
isolated electrically by a trench isolation
102
. Monitor transistor MT is a MOS (Metal Oxide Semiconductor) transistor and include a pair of source/drain regions
103
, a gate insulating layer
104
and a gate electrode layer
105
.
A pair of source/drain regions
103
are formed spaced apart from each other on the surface of silicon substrate
101
and have an LDD (Lightly Doped Drain) structure. Gate electrode layer
105
is formed on a region sandwiched by source/drain regions
103
of the pair with gate insulating layer
104
interposing therebetween. Insulating layers
106
and
107
are formed so as to cover the top and side surfaces of gate electrode layer
105
.
An interlayer insulating layer
108
is formed so as to cover plural monitor transistors MT and has holes
108
a
reaching to source/drain regions
103
formed therein. Holes
108
a
are each filled with a pad layer
109
b
or
109
c.
An interlayer insulating layer
110
is formed on interlayer insulating layer
108
and has a hole
110
a
reaching pad layer
109
b
formed therein.
A lead interconnection layer
111
a
is formed on interlayer insulating layer
110
so as to be electrically connected to pad layer
109
b
through hole
110
a.
Furthermore, plural conductive layers
111
are formed on interlayer insulating layer
110
in addition to lead interconnection layer
111
a.
An interlayer insulating layer
112
is formed so as to cover lead interconnection layer
111
a
and plural conductive layers
111
. Interlayer insulating layer
112
and interlayer insulating layer
110
have a hole
112
a
reaching pad layer
109
c
therethrough, and a plug layer
113
is formed in holes
112
a.
An interlayer insulating layer
114
is formed on interlayer insulating layer
112
and has a hole
114
a
formed therein. A lead interconnection layer
115
a
is formed along an inner wall of hole
114
a
and electrically connected to pad layer
109
c
through plug layer
113
. Note that a conductive layer
115
serving as many dummy storage nodes is formed in addition to lead interconnection layer
115
a.
There are formed an insulating layer
116
constituted of the same layer as is a capacitor dielectric layer and a conductive layer
117
constituted of the same layer as is a cell plate so as to cover an upper surface of lead interconnection layer
131
, and an insulating layer
118
is formed on conductive layer
117
.
In order to monitor a characteristic of monitor transistor MT, source/drain regions
103
of a pair are lead out by respective lead interconnection layers
111
a
and
115
a.
Lead interconnection layers
111
a
and
115
a
are electrically connected to bonding pad layers, which is the uppermost layer.
In order to monitor a characteristic of a prior art monitor transistor MT, a monitor signal is inputted from a bonding pad exposed on a wafer surface after all the wafer process is over. The monitor signal is given to a pair of source/drain regions
103
of monitor transistor MT from the bonding pad through lead interconnection layer
111
a
or
115
a,
and thereby, the characteristic of monitor transistor MT is monitored.
Along with progress in miniaturization of a semiconductor device, especially a DRAM, in structure in recent years, however, it has been requested to monitor a characteristic of a memory cell transistor with more of correctness. For example, parasitic resistance of lead sections of source/drain regions
103
of a monitor transistor MT and direct contact resistance parasitizing source/drain regions
103
should be considered so as to be the smallest possible value since such parasitic resistance works as obstacles in correct evaluation of a transistor characteristic.
Furthermore, in order to perform quick feedback in development of a semiconductor device, a transistor characteristic is desirably evaluated not only in the final stage of a wafer process but also at a stage, particularly as early as possible, into a wafer process from the start thereof.
SUMMARY OF THE INVENTION
The present invention has been made in order to respond to a request as described above, and it is accordingly, an object of the present invention to provide a semiconductor device capable of monitoring a transistor characteristic correctly and easily by reducing parasitic resistance, further, at an early stage in a wafer process; and a method of manufacturing therefor.
A semiconductor device of the present invention is a semiconductor device having a monitor pattern for measuring a characteristic of a memory cell transistor included in a memory cell, having a monitor transistor; a first lead interconnection layer; and a second lead interconnection layer. The monitor transistor has a source impurity region and a drain impurity region. The first lead interconnection layer is electrically connected to the source impurity region and has a section to which a needle of a prober can be connected externally. The second lead interconnection layer is electrically connected to the drain impurity region and has a section to which a needle of a prober can be connected externally. The first and second lead interconnection layers are formed on the same layer and further, formed on the same layer as is one of a bit line conductive layer and a storage node conductive layer, electrically connected to the memory cell transistor.
According to a semiconductor device of the present invention, since the first and second lead interconnection layers have each sections to each of which the needle of a prober can be connected and are formed on the same layer as are a bit line and a storage node, a transistor characteristic can be monitored at a stage where the bit line and the storage node of a memory cell have been formed. Accordingly, since monitoring of a transistor characteristic can be performed at an early stage in a wafer process, thereby enabling quick feedback in development of a semiconductor device.
Furthermore, since no necessity arises for leading out the source and drain regions of a monitor transistor to the bonding pads in the uppermost layer, dissimilar to the prior art example, it is possible to reduce parasitic resistance of lead sections thereof, which makes it possible to monitor a transistor characteristic correctly and easily.
In the above semiconductor device, a material of the first and second lead interconnection layers are preferably made from metal.
With adoption of metal as material of the interconnection layers, the parasitic resistance of the lead sections can be further reduced, thereby ena
Renesas Technology Corp.
Tran Minhloan
Tran Tan
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