Semiconductor device having a low-resistivity planar wiring stru

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257308, 257384, H01L 2968, H01L 2348, H01L 2904

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active

052006352

ABSTRACT:
The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.

REFERENCES:
patent: 4674176 (1987-06-01), Tuckerman
patent: 4974055 (1990-11-01), Haskell
patent: 4994893 (1991-02-01), Ozaki et al.
patent: 5012309 (1991-04-01), Nakayama
patent: 5045899 (1991-09-01), Arimoto
IEEE Transactions on Electron Devices, vol. 38, No. 2, Feb. 1991, pp. 255-261.
1990 Symposium on VLSI Technology (IEEE), pp. 13-14.

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