Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-11-22
2004-10-05
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S652000, C438S653000, C438S655000, C438S656000, C438S658000, C438S664000, C438S683000
Reexamination Certificate
active
06800543
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a lower-resistance gate electrode and a method for manufacturing such a semiconductor device.
2. Description of the Related Art
In large-scale integrated circuits (LSIs), a variety of gate structures are developed in order to realize a gate electrode having a lower resistance for achieving a higher operational speed. For example, a metallic gate electrode made of aluminum (Al) deposited on a gate oxide film has the advantage of lower resistance. However, this metallic gate electrode suffers from the disadvantage of lower heat resistance at higher temperature ranges. Thus, such a gate electrode is not suited for a self-alignment structure where the gate electrode must be formed before a thermal treatment at a higher temperature.
A silicon gate electrode made of doped polysilicon (DOPOS) formed on a gate oxide film is also known as a low-resistance gate electrode. Such a DOPOS gate electrode can be formed on the gate oxide film at an earlier stage of a fabrication process for the semiconductor device, for example, directly after formation of the gate oxide film, whereby it is suited for the self-alignment process. The DOPOS gate electrode has an additional advantage that contamination of the gate oxide film by dusts can be prevented; however, it has the advantage of a higher sheet resistance of the DOPOS and there is an inevitable limit on achieving a lower-resistance gate electrode.
There is also a known low-resistance gate electrode having a polycide structure, wherein a high-melting-point metal (refractory metal) silicide layer is deposited on a thin DOPOS film formed on a gate oxide film, for achieving a lower-resistance gate electrode. The polycide gate electrode has the advantages of higher heat resistance which is suited for the self-alignment process, a non-reaction property of the polycide gate with the gate oxide film and so on. However, the polycide gate structure also has the disadvantage of higher sheet resistance, and thus there is a limit on the achievement of a low-resistance gate electrode.
Another gate electrode structure is also known for achieving a lower-resistance gate electrode, wherein a refractory metal layer such as made of tungsten is formed on a thin DOPOS film. This gate electrode structure has lower sheet resistance compared to the silicon gate electrode, thereby improving the response speed of a MOS device. However, in this structure, the refractory metal layer reacts with the DOPOS film to form a silicide of the refractory metal, such as WSi
2
, similar to the polycide gate structure, and accordingly, there is a limit on further reduction of the resistance of the gate electrode. In addition, there are other disadvantages of reduction in the impurity concentration of the DOPOS film and diffusion of the metallic atoms from the refractory metal layer.
Patent Publication JP-A-11-233451 describes a technique for suppressing the reaction between the refractory metal layer and the DOPOS film at a high temperature range by interposing therebetween a refractory metal nitride layer. In the described technique, a heat treatment is conducted after the refractory metal nitride layer is formed on the DOPOS film, thereby removing the excessive nitrogen component in the refractory metal nitride layer and converting the entire refractory metal nitride layer into a refractory metal silicide nitride layer.
In the technique described in the publication, the heat treatment conducted to the refractory metal nitride layer formed on the DOPOS film causes a strong reaction between the refractory metal nitride layer and the DOPOS film, whereby a thick refractory metal silicide nitride layer is formed. Although the refractory metal silicide nitride layer generally has a higher barrier function, a higher thickness for the refractory metal silicide nitride layer has a tendency to suppress the reduction in the resistance of the gate electrode structure, because the refractory metal silicide nitride layer has a higher interface resistance depending on the composition and the film structure thereof. Thus, there is a limit on the reduction in the resistance of the gate electrode.
SUMMARY OF THE INVENTION
In view of the above problem in the conventional techniques, it is an object of the present invention to provide a method for manufacturing a semiconductor device having a low-resistance gate electrode structure including a DOPOS film and a refractory metal silicide nitride layer.
It is another object of the present invention to provide such a semiconductor device.
The present invention provides a method for manufacturing a gate electrode in a semiconductor device, including the steps of: forming a layer structure including a doped polysilicon (DOPOS) film, a silicide film including a first refractory metal, a nitride film including the first refractory metal, and a metallic film including a second refractory metal, consecutively as viewed from a substrate; and heat treating the layer structure as a whole.
The present invention also provides a semiconductor device including a substrate, and a gate electrode structure overlying the substrate, the gate electrode structure including a doped polysilicon (DOPOS) film, a silicide film including a first refractory metal, a nitride film including the first refractory metal, and a metallic film including a second refractory metal, consecutively as viewed form the substrate.
In accordance with the semiconductor device manufactured by the method of the present invention and the semiconductor device of the present invention, the refractory metal silicide nitride film formed in the gate electrode structure by the heat treatment conducted to the gate electrode structure as a whole has a smaller thickness compared to the conventional refractory metal silicide nitride film, and thus has a smaller interface resistance, thereby achieving a higher operational speed for the semiconductor device.
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Wolf, Ph.D., Stanley, “Hot-Carrier-Resistant Processing and Device Structures,” Silicon Processing for the VLSI Era—vol. 3: The Submicron MOSFET, Lattice Press, 1995, pp. 595-598.
Elpida Memory Inc.
Hayes & Soloway P.C.
Thomas Toniae M.
Wilczewski Mary
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