Semiconductor device having a high breakdown voltage

Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – With electric field controlling semiconductor layer having a...

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257492, 257339, 257350, 257656, H01L 2936

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active

058747680

ABSTRACT:
A high breakdown voltage semiconductor device formed in an SOI structure is disclosed. An MOS transistor composed of a drift layer, p well, a source, a gate, and a drain is formed in an island region surrounded by insulators on a semiconductor substrate. Furthermore, an electricfield-alleviating layer is formed in a bottom portion of the Si island region. The electric-field-alleviating layer is a semiconductor layer of exceeding low concentration, e.g., intrinsic, and therefore a virtual PIN structure is structured among the p well and the drift layer. Because the electric-field-alleviating layer corresponds to an I layer of the PIN structure, a depletion layer is created within the electric-field-alleviating layer when high voltage is applied to the MOS transistor, the high voltage is distributed throughout this depletion layer, and high breakdown voltage can be obtained.

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patent: 5241210 (1993-08-01), Nakagawa et al.
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Pierret, Robert F.; "Semiconductor Fundamentals," vol. 1, 2nd Ed., 1988, p. 71.
T. Matsudai, et al. "Simulation of a 700 V High-Voltage Device Structure on a Thin SOI", Proceedings of 1992 International Symposium on Power Semiconductor Devices & IC's, Tokyo, pp. 272-277.

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