Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-06-11
2002-06-04
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S132000, C438S215000, C438S281000, C438S467000
Reexamination Certificate
active
06399472
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having fuse patterns and a fuse window cooperating therewith such that the fuse patterns are selectively blown by irradiating a laser beam through the fuse window.
BACKGROUND ART
With the advancement in the art of device miniaturization, the effect of defective device elements in a semiconductor integrated circuit on the overall production yield of the integrated circuit is increasing. This problem is particularly serious in large-capacity LSI memory devices of very large total number of bits such as 64 Mbit DRAMs (dynamic random access memories). Because of this problem, such large capacity LSI memory devices generally use a redundant construction in which a plurality of redundant memory cell rows or a plurality of redundant memory cell columns are provided in a memory cell array. Further, such a redundant construction generally includes a fuse typically formed of polysilicon. Thus, when a memory cell row or memory cell column containing a defective bit is to be replaced with a redundant memory cell row or a redundant memory cell column, or when to conduct other desired functional selection, it has been practiced to selectively blow a suitable fuse pattern by a laser beam or by an electrical current.
It should be noted that such a fuse pattern is generally surrounded by various semiconductor circuit elements and interconnection layers. In recent highly integrated semiconductor devices, the interconnection layer extends to the region in the vicinity of the fuse pattern, and because of this, there tends to arise the problem of poor planarization in the protective film covering the interconnection patterns in the interconnection layer when the width or pitch of the interconnection layer is reduced. When the planarization of the protective film is thus deteriorated, the step coverage of the interconnection patterns by the protective film is deteriorated, leading to void formation. Such a formation of void in the protective film causes the problem of poor resistance of the integrated circuit against moisture. Thus, in order to improve the resistance against moisture, various efforts are being made to improve the planarization of the protective film by using various protective films.
In the case when a highly planarized protective film is formed to cover the fuse, on the other hand, there inevitably arises the problem of local variation in the thickness of the protective film due to the step caused by the existence of the fuse pattern. In other words, it is difficult to cover the fuse patterns by the protective film with a uniform thickness. Further in view of the recent tendency of increase in the diameter of the semiconductor wafer, the change in the thickness of the protective film over the wafer surface is increasing. Thereby, the thickness of the protective film may change in the semiconductor chips even when the semiconductor chips are obtained from a single wafer. Further, there may be a variation in the thickness of the protective film for the different fuse patterns formed in a single semiconductor chip.
FIGS. 1A-1C
show a conventional process of forming a fuse window.
Referring to
FIG. 1A
, a p-type Si substrate
41
is covered by an oxide film
42
and a plurality of fuse patterns
43
are formed by a patterning process of a polysilicon layer. After the formation of the fuse patterns
43
, an SiO
2
film
44
is deposited thereon by a CVD process so as to cover the fuse patterns
43
, and an Al alloy film is deposited on the SiO
2
film
44
by a PVD (physical vapor deposition) process such as a sputtering process or an evaporation deposition process. By patterning the Al alloy film thus deposited, an interconnection pattern
45
and a bonding pad
46
are formed. Next, the SiO
2
film
44
is covered by another SiO
2
film
47
deposited by a PCVD (plasma CVD) process so as to cover the interconnection pattern
45
and the bonding pad
46
, and an SOG film is formed on the SiO
2
film
47
by a spin coating process. After a heat treatment process and an etch-back process conducted by an RIE (reactive ion etching) process on the SOG film thus deposited, there is obtained a planarized structure in which the depressed part is filled with an SOG film
48
. The SOG film
48
remains also adjacent to the stepped part. Further, a protective film
49
of SiN is deposited on the planarized structure by a PCVD process.
Next, in the step of
FIG. 1B
, a fuse window
51
and a bonding opening
52
exposing the bonding pad
46
are formed simultaneously in the SiN film
49
by an RIE process while using a resist pattern
50
as a mask, wherein the duration of the etching process is controlled such that an SiO
2
film
44
remains on the fuse patterns
43
.
Next, in the step of
FIG. 1C
, the resist pattern
50
is removed and a predetermined electrical interconnection is made at the foregoing bonding opening
52
, and a laser irradiation process is conducted subsequently in which a laser beam is applied to a selected fuse pattern
43
corresponding to the necessary redundant circuit via the fuse window
51
such that the selected fuse pattern
43
is blown by the laser beam. The fuse pattern
43
may also be the one that selects a desired circuit function.
In the foregoing conventional process, it should be noted that the thickness of the insulation film remaining on the fuse patterns
43
may change variously due to the local variation in the thickness of the insulation film
44
covering the fuse patterns
43
, wherein it should be noted that the foregoing local variation is caused as a result of the foregoing planarization process. When such a variation occurs in the thickness of the insulation film
44
covering various fuse patterns
43
, there arises a problem in that some fuse pattern
43
is easily blown up by the laser beam irradiation while some are not. Thereby, it becomes difficult to blow the selected fuse pattern by the laser beam with reliability.
FIGS. 2A-2D
show another conventional process of forming a fuse window in which a uniform thickness is guaranteed for the insulation film covering the fuse patterns
43
. In
FIGS. 2A-2D
, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to
FIG. 2A
, the fuse patterns
43
of polysilicon are formed on the oxide film
42
covering the p-type Si substrate
41
similarly as in the case of
FIG. 1A
, and the fuse patterns
43
are covered by the SiO
2
film
44
deposited by a CVD process. Further, an Al alloy film is deposited on the SiO
2
film
44
by a sputtering process or an evaporation deposition process, followed by a patterning process to form the interconnection pattern
45
and the bonding pad
46
, similarly as before. The interconnection pattern
45
and the bonding pad
46
are then covered by the SiO
2
film
47
deposited by a PCVD process, and an SOG film is formed on the SiO
2
film
47
by a spin coating process. Next, the SOG film thus deposited is subjected to a curing process, followed by an etch-back process conducted by an RIE process, to form a planarized structure in which the SOG film
48
fills the depressions or steps. Further, the SiN film
49
is deposited on the planarized structure thus obtained by a PCVD process as a protective film.
Next, in the step of
FIG. 2B
, the fuse window
51
and the bonding opening
52
are formed simultaneously by an RIE process while using the resist pattern
50
as a mask, wherein the fuse window
51
is formed such that the SiO
2
film
44
is removed entirely from the fuse window
51
.
In
FIG. 2B
, it may seem that the exposed surface of the oxide film
42
is entirely flat. In the actual structure, the oxide film
42
experiences an etching action, and because of this, the surface of the exposed oxide film
42
tends to show slight projection or depression reflecting the thickness variation of the insulation film on th
Adachi Kazuhiro
Hayashi Manabu
Hideshima Osamu
Katayama Masaya
Kawabata Ken-ichi
Armstrong Westerman & Hattori, LLP
Lytle Craig P.
Smith Matthew
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