Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-03-27
2003-10-28
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S230030
Reexamination Certificate
active
06639855
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2001-348723, filed on Nov. 14, 2001, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and the present invention is particularly suitable for a semiconductor device including a plurality of semiconductor memory circuits and having a defect relief function of relieving a failure due to a defect in the semiconductor memory circuit.
2. Description of the Related Art
Recently, with an improvement in semiconductor process technology and the like, large-scale integration, high-density design, and high performance of a semiconductor device are remarkable, and, for example, the total memory size of semiconductor memory circuits which can be provided in one semiconductor device (a semiconductor chip serving as one function) has been increasing. The increase in the total memory size of the semiconductor memory circuits in the semiconductor device increases the number of elements to be formed on the semiconductor chip and increases the probability of occurrence of defects per one semiconductor device, and hence this is one of causes of a reduction in the yield rate of the semiconductor device.
As one of methods for improving the yield rate of the semiconductor device including the semiconductor memory circuits, the addition of a defect relief function to the semiconductor memory circuit is generally performed. As for the addition of the defect relief function to the semiconductor memory circuit, a redundant circuit composed of a redundant memory cell (memory cell for relieving a defect) and its peripheral circuit (for example, a decode circuit, a sense amplifier circuit, and switches for selecting whether or not the redundant memory cell is used) are added to each of the semiconductor memory circuits. A failure due to a defect or the like is detected in the semiconductor memory circuit, a circuit portion where the failure exists is switched to the redundant circuit, and the redundant circuit (redundant memory cell and its peripheral circuit) is used in place of the circuit portion where the failure is used. As a result, even if the failure exists in the semiconductor memory circuit, a function as an ordinary semiconductor memory circuit is satisfied and operated normally.
The semiconductor memory circuit having the defect relief function as described above can maintain the function as the ordinary semiconductor memory circuit by using the redundant circuit (utilizing the defect relief function) in place of the circuit portion where the failure exists, even if the failure due to the defect and the like exists in the semiconductor memory circuit to some extent. Hence, by adding the defect relief function (redundant circuit) to the semiconductor memory circuit, the yield rate of the semiconductor device including the semiconductor memory circuits can be improved.
Concerning the conventional semiconductor memory circuit having the defect relief function, however, the redundant circuit composed of the redundant memory cell and peripheral circuit incidental to the redundant memory cell is added to each semiconductor memory circuit. Accordingly, there is a problem that by the addition of the redundant circuit, the semiconductor memory circuit having the defect relief function becomes larger in circuit area than the semiconductor memory circuit having no defect relief function.
In this case, the redundant circuit is used only when relieving the failure due to the defect, and hence the redundant circuit wastes the circuit area when the semiconductor memory circuit does not need defect relief, that is, the semiconductor memory circuit is a non-defective in which no failure due to a defect exists.
Moreover, the memory cell portion of the semiconductor memory circuit is crowded with a large number of transistors, whereby wiring (wiring pattern) is formed at high density, and in addition, weak signals different from signals in an ordinary logic circuit are often used. As a result, the memory cell portion of the semiconductor memory circuit tends to become faulty (malfunction) even in the case of a small defect. Therefore, in the semiconductor memory circuit, failures caused by defects tend to concentrate in the memory cell portion.
Accordingly, the redundant memory cell actually relieves the failure due to the defect and has a high effect on an improvement in the yield rate of the semiconductor device having semiconductor memory circuits. Meanwhile, the peripheral circuit incidental to the redundant memory cell primarily plays a role in realizing the defect relief function, and practically has little effect on the relief of the failure due to the defect and the improvement in the yield rate of the semiconductor device.
Especially when a large number of semiconductor memory circuits each with a small memory size having the defect relief function are mounted on one semiconductor device, the memory size of each semiconductor memory size is small (the memory cell portion is small), and hence the possibility of existence of the failure due to the defect in each of the semiconductor memory circuits is low, whereby the redundant circuits often become wastes. Moreover, by adding the redundant circuits respectively to the semiconductor memory circuits with the small memory size, the circuit areas of the peripheral circuits incidental to the redundant memory cells and having little practical effect on defect relief increase, whereby the proportion of the circuit areas of the peripheral circuits incidental to the memory cells increases with respect to the circuit areas of the memory cell portions where the failure due to the defect tends to occur.
When one semiconductor device includes a large number of semiconductor memory circuits each having the defect relief function as described above, the yield rate of the semiconductor device improves by the addition of redundant circuits (defect relief functions), but the chip area (circuit area) of the semiconductor chip on which the semiconductor device is formed increases. Hence, the yield of semiconductor devices (number of semiconductor devices capable of being produced per unit material) decreases, and consequently an improvement in the acquisition rate of non-defectives per unit material is hindered.
Namely, even if the yield rate of the semiconductor device including the semiconductor memory circuits improves by adding the redundant circuits, the acquisition rates of non-defective semiconductor devices per unit material often decreases because of an increase in circuit area due to the addition of the redundant circuits.
SUMMARY OF THE INVENTION
It is an object of the present invention to add a defect relief function to each of a plurality of semiconductor memory circuits without impairment of the defect relief function while suppressing an increase in circuit area.
A semiconductor device of the present invention comprises a plurality of semiconductor memory circuits respectively operating based on different address signals and a redundant circuit shared between the plurality of semiconductor memory circuits. The redundant circuit is allowed to operate as a portion in any one of the semiconductor memory circuits according to redundant relief information on the semiconductor memory circuits.
According to the present invention having the configuration as described above, by sharing the redundant circuit between the plurality of semiconductor memory circuits, the defect relief function can be added to each of the plurality of semiconductor memory circuits while reducing a circuit area required for the addition of the redundant circuit per one semiconductor memory circuit.
REFERENCES:
patent: 5576999 (1996-11-01), Kim et al.
patent: 5715202 (1998-02-01), Harima
patent: 5892718 (1999-04-01), Yamada
patent: 6151259 (2000-11-01), Hori
Arent Fox Kintner Plotkin & Kohn
Fujitsu Limited
Mai Son
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