Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-07-17
2001-09-11
Le, Dieu-Minh (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S045000, C714S047300
Reexamination Certificate
active
06289473
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a system LSI having a debug function.
2. Description of the Background Art
A semiconductor device forming a predetermined system by a combination of a plurality of integrated circuits (modules) having various functions, that is, a system LSI stores software (a program) and hardware (for example, a hard-wired logic) which define an operation thereof. Whether or not the software and the hardware have errors is checked by a debugging operation which is important to a process of developing and manufacturing the system LSI.
FIG. 7
shows a general structure of the system LSI. The system LSI shown in
FIG. 7
comprises a CPU (central processing unit)
1
, a first processor
2
, a second processor
3
, an IO (input-output) processor
4
and a memory
5
. These modules are connected through a bus line
6
, and receive and send a signal therebetween.
An example of the operation of the system LSI will be described below. Data input from the outside is stored in the memory
5
through the IO processor
4
. The CPU
1
, the first processor
2
and the second processor
3
exchange the input data through the memory
5
, perform predetermined processings and finally output the processed data to the outside.
Since the CPU
1
, the first processor
2
and the second processor
3
perform processings for the input data at the same time, they operate independently and are mutually synchronized with each other if necessary. For example, in a case where a program stored in the CPU
1
is debugged in such an operating situation, the operation of the CPU
1
is stopped to interrupt a special program for debugging into the CPU
1
and to check the operating state. In this case, it is also necessary to stop the operations of the first processor
2
, the second processor
3
and the IO processor
4
. For this reason, a stop signal SS is sent from the CPU
1
to these modules.
In the conventional system LSI, thus, an operation of each module is simply stopped in response to the stop signal sent from the CPU
1
simultaneously with the suspension of the operation of the CPU
1
. Therefore, the conventional system LSI cannot deal with complicated debug patterns. As described above, each module operates independently. For this reason, it is hard to stop their operations at the same time. The conventional system LSI has not had a structure in which the outside is caused to know whether or not the operations of the first and second processors
2
and
3
are also stopped when the program stored in the CPU
1
is stopped. Therefore, if a program for debugging is input from a microcomputer provided on the outside or the like in order to execute the debugging for the program stored in the CPU
1
in a state in which the first and second processors
2
and
3
continue the operations, the first and second processors
2
and
3
are sometimes broken (on a software or hardware basis).
For example, even if the program stored in the CPU
1
is stopped in a predetermined specific portion to stop the operations of the first and second processors
2
and
3
, the operations of the first and second processors
2
and
3
are not stopped immediately but after a predetermined time has passed because they are not generally stopped before a predetermined processing is completed. Accordingly, there have been the following problems. It is impossible to know internal states of the first and second processors
2
and
3
immediately after the operation of the CPU
1
is stopped. Even if the first and second processors
2
and
3
are reactivated to give data or an operation instruction from the CPU
1
, the internal states of the first and second processors
2
and
3
progress more than those obtained immediately after the operation of the CPU
1
is stopped so that the first and second processors
2
and
3
are not ready to accept the data or operation instruction. Therefore, they ignore the data or operation instruction sent from the CPU
1
to continue a wrong operation or to cause hang-up. However, each module has not had a structure to eliminate such drawbacks.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a semiconductor device comprising a first processor, at least one second processor for receiving and sending a signal from/to the first processor, and a debug control circuit for outputting a stop signal to give an instruction for stop of an operation during debugging of respective systems to the first processor and the at least one second processor, the at least one second processor being controlled by the first processor and individually operating independently of the first processor, the first processor and the at least one second processor outputting a trigger signal which requires to output the stop signal to the debug control circuit when performing first predetermined specific operations respectively, and outputting a stop detecting signal indicative of stop to the debug control circuit when the operation is stopped in response to the stop signal, and the debug control circuit outputting the stop signal on receipt of the trigger signal, and outputting a stop notice signal indicative of stop of all of the first processor and the at least one second processor if the stop detecting signal is output from all of the first processor and the at least one second processor.
A second aspect of the present invention is directed to the semiconductor device wherein the first processor and the at least one second processor further have a function of bringing, into a significant condition, and outputting one of a trigger excluding signal negating that the stop signal is brought into a significant condition and a trigger accepting signal permitting the stop signal to be brought into a significant condition to the debug control circuit when the first processor and the at least one second processor perform predetermined specific second operation other than the first specific operation, respectively, and the debug control circuit further has functions of negating that the stop signal is brought into a significant condition even if it receives the trigger signal in a case where the trigger excluding signal is input, and bringing the stop signal into a significant condition on receipt of the trigger signal in a case where the trigger accepting signal is input.
A third aspect of the present invention is directed to the semiconductor device wherein the debug control circuit comprises a first circuit for receiving the trigger signals output from the first processor and the at least one second processor, and for bringing, into a significant condition, and outputting a first signal if at least one of the trigger signals is in a significant condition, a second circuit for receiving the trigger accepting signals output from the first processor and the at least one second processor, and for bringing, into a significant condition, and outputting a second signal if at least one of the trigger accepting signals is in a significant condition, a third circuit for receiving the trigger excluding signals output from the first processor and the at least one second processor, and for bringing, into a significant condition, and outputting a third signal if at least one of the trigger excluding signals is in a significant condition, a fourth circuit for receiving the stop detecting signals output from the first processor and the at least one second processor, and for bringing, into a significant condition, and outputting a fourth signal if all of the stop detecting signals are in a significant condition, a fifth circuit for receiving the second and third signals, and for outputting a trigger acceptance deciding signal which is brought into a significant condition when the second signal is in a significant condition and into a nonsignificant condition when the third signal is in a significant condition, a sixth circuit for receiving the first signal and the trigger acceptance decidin
Burns Doane , Swecker, Mathis LLP
Le Dieu-Minh
Mitsubishi Denki & Kabushiki Kaisha
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