Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2005-10-25
2005-10-25
Phan, Trong (Department: 2827)
Static information storage and retrieval
Addressing
Multiple port access
C365S230060, C365S189050
Reexamination Certificate
active
06958948
ABSTRACT:
The current consumed by latching data and during standby are significantly decreased in order to realize reduced power consumption. In this memory cell, source voltages VRETand VDDare supplied to latch circuit10and output circuit32from different systems. Latch circuit10can be separated from a peripheral circuit by NMOS transistor20and transmission gate24.MOS transistors12, 14, 16,and18,which constitute latch circuit10and MOS transistors20, 26,and28,which constitute the switch circuit, are configured using low-leakage MOS transistors with leakage current significantly lower than those of standard MOS transistors used to configure the peripheral circuit including output circuit32.
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Brady III W. James
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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