Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-04-30
2004-08-10
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000
Reexamination Certificate
active
06774423
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising a capacitor.
2. Description of the Background Art
In general, a conventional semiconductor device includes a transistor and a capacitor formed on the transistor along a hole extending perpendicularly to the main surface of a semiconductor substrate. In this capacitor, the aforementioned hole is generally provided to pass through a multilevel insulator film stacked on the transistor.
In the structure of such a conventional capacitor, it may be impossible to provided further away the position of an upper portion of the hole in which a capacitor is formed from the main surface of the semiconductor substrate. In this case, the capacitance of the capacitor cannot be increased. Consequently, refreshability and soft error resistance of the semiconductor device cannot be improved.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device capable of improving refreshability and soft error resistance also when the position of an upper portion of a hole in which a capacitor is formed cannot be provided further away from the main surface of a semiconductor substrate.
A semiconductor device comprises a transistor provided on a semiconductor substrate, a first etching stopper film formed to cover the transistor and a first insulator film formed on the first etching stopper film.
The semiconductor device also comprises a second etching stopper film formed on the first insulator film to cover the transistor and a second insulator film formed on the second etching stopper film.
The semiconductor device further comprises a capacitor electrically connected to the transistor above the second insulator film.
A lower electrode, a dielectric film and an upper electrode of the capacitor are sequentially formed in a hole extending perpendicularly to the main surface of the semiconductor substrate along the surface of the hole.
The hole passes through the second insulator film, the second etching stopper film and the first insulator film. The bottom surface of the hole is located below the main surface of the first stopper film.
According to the aforementioned structure, the height of the hole extending perpendicularly to the main surface of the semiconductor substrate between the semiconductor substrate and a wiring part of a memory cell part can be maximized as compared with a hole, formed with the capacitor, located above the main surface of the second etching stopper film.
Consequently, the surface area of the lower electrode of the capacitor formed along the surface of the hole can be maximized also when the upper portion of the hole cannot be provided further away from the semiconductor substrate. According to the aforementioned semiconductor device, therefore, the capacitance of the capacitor can be maximized.
A semiconductor device according to a second aspect of the present invention comprises a semiconductor substrate and a first insulator film formed above the semiconductor substrate to extend substantially in parallel with the main surface of the semiconductor substrate.
The semiconductor device also comprises a first hole passing through the first insulator film perpendicularly to the main surface of the semiconductor substrate and a second insulator film formed on the first insulator film.
The semiconductor device further comprises a second hole located inside the opening of the first hole to pass through the first insulator film perpendicularly to the main surface of the semiconductor substrate.
In the aforementioned structure, a capacitor lower electrode is formed over the entire inner side surface of the first hole along the inner side surface.
According to the aforementioned structure, the surface area of the capacitor lower electrode can be maximized in the first hole without further providing away the upper portion of the first hole from the main surface of the semiconductor substrate. Therefore, the capacitance of a capacitor can be maximized when the upper portion of the hole formed with the capacitor cannot be provided away from the main surface of the semiconductor substrate.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6583461 (2003-06-01), Yokoyama et al.
patent: P2001-196553 (2001-07-01), None
Pham Hoai
Pham Long
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