Semiconductor device having a capacitor with a multi-layer...

Details Semiconductor device having a capacitor with a multi-layer... Semiconductor device having a capacitor with a multi-layer...

2000-12-20

2004-02-10

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000

Reexamination Certificate

active

06690052

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to a semiconductor memory device incorporating therein high K dielectric as a capacitor dielectric film.
DESCRIPTION OF THE PRIOR ART
As is well known, a dynamic random access memory (DRAM) with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
To meet the demand, there have been proposed several structures for the capacitor, such as a trench type or a stack type capacitor, which are arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.
In attempt to meet the demand, there have been introduced a high K dielectric, e.g., Ta
2
O
5
or the like, as a capacitor thin film in place of conventional silicon oxide film or silicon nitride film. Since, however, a Ta
2
O
5
layer is grown with a columnar structure during a following heat-treatment process, the grown Ta
2
O
5
layer becomes a high leakage current. Therefore, it is very difficult for applying the Ta
2
O
5
layer to a capacitor thin film for use in memory device.
Alternatively, a multi-layer dielectric, e.g., Ta
2
O/TiO
2
or Ta
2
O/Al
2
O
3
, has been proposed to use as a capacitor thin film by using a metal organic chemical deposition (MOCVD) to overcome the above-described problem. However, the MOCVD method makes a foreign material reside in the capacitor thin film. This result enforces the capacitor thin film to be performed a high temperature heat-treatment, which, in turn, generates a defect and a high leakage current in the capacitor thin film.
There are still demands for developing a high K dielectric having a low leakage current which is compatible with a semiconductor process.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor device incorporating therein a high K dielectric as a capacitor dielectric.
It is another object of the present invention to provide a method for manufacturing a semiconductor device incorporating therein a high K dielectric as a capacitor dielectric.
In accordance with one aspect of the present invention, there is provided a semiconductor device for use in a memory cell, comprising: an active matrix provided with a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate and conductive plugs electrically connected to the transistors; a number of bottom electrodes formed on top of the conductive plugs; composite films formed on the bottom electrodes; and Al
2
O
3
films formed on the composite films.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of: a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; b) forming a conductive layer on top of the active matrix; c) patterning the conductive layer a predetermined configuration, thereby obtaining a number of bottom electrodes; d) forming a (Ta
2
O
5
)
x
(TiO
2
)
y
composite layer on the bottom electrodes, x and y representing a molar fraction, respectively; e) forming a dielectric layer on the (Ta
2
O
5
)
x
(TiO
2
)
y
composite layer; and f) patterning the dielectric layer and the (Ta
2
O
5
)
x
(TiO
2
)
y
composite layer into a preset configuration, thereby obtaining the semiconductor device.


REFERENCES:
patent: 5561307 (1996-10-01), Mihara et al.
patent: 5621606 (1997-04-01), Hwang
patent: 5847424 (1998-12-01), Kang
patent: 5923524 (1999-07-01), Cava
patent: 5926710 (1999-07-01), Tseng
patent: 6144060 (2000-11-01), Park et al.
patent: 2000-058777 (2000-02-01), None

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