Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-24
2003-02-11
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S331000, C257S345000, C257S402000, C257S403000, C257S409000
Reexamination Certificate
active
06518623
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a buried-channel MOS structure in the main surface of a semiconductor substrate and a manufacturing method thereof.
2. Description of the Background Art
With the recent higher integration of semiconductor devices typically including SRAMs and DRAMs, an increasing number of elements are fabricated on a single chip. These elements mostly include, particularly as transistors, field-effect transistors called MOSFETs (Metal Oxide Silicon Field Effect Transistors). The MOSFETs include nMOSFETs (negative MOSFETs) where electrons carry current and pMOSFETs (positive MOSFETs) where holes carry current; the nMOSFETs and pMOSFETs have different electric polarities. Various kinds of circuits are constructed using combinations of nMOSFETs and pMOSFETs.
Known structures of MOSFETs include the surface channel type shown in FIG.
29
and the buried channel type shown in FIG.
30
. In the semiconductor device
151
shown in
FIG. 29
, the semiconductor substrate
100
has source/drain layers
12
separated at an interval (a pair of a source layer and a drain layer are generically called source/drain layers), a punch-through stopper layer
4
, and element isolation regions
2
for isolating a plurality of elements. The source/drain layers
12
and the punch-through stopper layer
4
have opposite conductivity types. The semiconductor layer
1
is left under the punch-through stopper layer
4
as part of the semiconductor substrate
100
.
A gate electrode
7
faces the space between the source/drain layers
12
with an insulating film
6
interposed between them. The gate electrode
7
has insulator spacers
11
on its side surfaces. Source/drain electrodes
14
(a pair of a source electrode and a drain electrode are generically called source/drain electrodes) are connected to the source/drain layers
12
. The gate electrode
7
and the source/drain electrodes
14
are insulated from each other by an insulating layer
13
covering the main surface of, the semiconductor substrate
100
. In the semiconductor device
151
thus constructed, the surface portion of the punch-through stopper layer
4
which faces the gate electrode
7
functions as a channel region.
In the semiconductor device
152
shown in
FIG. 30
, the semiconductor substrate
100
further includes a counter doped layer
5
and a well layer
31
, in addition to the source/drain layers
12
, punch-through stopper layer
4
and element isolation regions
2
. The counter doped layer
5
has the same conductivity type as the source/drain layers
12
and the well layer
31
has the same conductivity type as the punch-through stopper layer
4
. The semiconductor layer
1
is left under the well layer
31
as part of the semiconductor substrate
100
. In the semiconductor device
152
thus constructed, a region around a PN junction between the counter doped layer
5
and the punch-through stopper layer
4
, which faces the gate electrode
7
, functions as the channel region. That is, the region spaced from the main surface functions as the channel region. This channel region is called “buried channel region.”
In these semiconductor devices
151
and
152
, the source/drain layers
12
and the channel region are formed by using impurity ion implantation or by using impurity diffusion from solid phase which contains the impurities. N-type diffusion layers contain N-type impurities such as phosphorus and arsenic and P-type diffusion layers contain P-type impurities such as boron.
Usually, in order to form the gate electrodes with the same material in nMOSFETs and pMOSFETs, nMOSFETs generally use the surface channel type and pMOSFETs use the buried channel type. Accordingly, in most cases, the semiconductor device
151
is formed as an nMOSFET as shown in FIG.
29
and the semiconductor device
152
is formed as a pMOSFET as shown in FIG.
30
.
FIGS. 31
to
36
are manufacturing process diagrams showing a method of manufacturing the semiconductor device
152
. In the manufacture of the semiconductor device
152
, first, the semiconductor substrate
100
is prepared and the element isolation regions
2
are formed in its main surface by LOCOS (Local Oxidation of Silicon) etc. (FIG.
31
). Next, phosphorus is implanted to form the N-type well layer
31
, and then phosphorus is implanted by ion implantation with an implantation energy of 100 keV to a dose of 6.0×10
12
ions/cm
2
or more, for example, to form the punch-through stopper layer
4
. Subsequently boron is implanted with an implantation energy of 20 keV and, as in the formation of the punch-through stopper layer
4
, to a dose of 6.0×10
12
ions/cm
2
or more, to form the counter doped layer
5
(FIG.
32
).
Next, a thermal oxidation is performed to form a 2- to 15-nm-thick film of oxide, as the insulating film
6
, on the main surface of the semiconductor substrate
100
. Subsequently, polycrystalline silicon
53
containing phosphorus at a concentration of 1×10
20
/cm
3
or more is deposited by LPCVD (Low Pressure CVD) to a thickness of 50 to 150 nm. Next, as an etching mask for formation of the gate electrode, a silicon oxide film
8
is deposited by CVD to a thickness of 20 nm, which is followed by formation of a resist pattern
9
used to form the gate electrode (FIG.
33
).
Next, using the resist pattern
9
as a mask, the silicon oxide film
8
and the polycrystalline silicon
53
are selectively etched to form the gate electrode
7
from the polycrystalline silicon
53
. The resist pattern
9
is then removed (FIG.
34
).
Next, an oxide film is deposited to a thickness of 50 to 100 nm to cover the entirety of the main surface of the semiconductor substrate
100
, which is etched back to form the insulator spacers
11
on the side surfaces of the gate electrode
7
(FIG.
35
).
Next, boron is implanted into the main surface of the semiconductor substrate
100
under the implant conditions of 5 to 30 keV and 1.0×10
15
ions/cm
2
, thus forming the P
+
source/drain layers
12
(FIG.
36
). Subsequently, a thermal process is performed at high temperature for activation and repair of crystal defects caused by the ion implantation during formation of the source/drain layers
12
. Next, referring to
FIG. 30
again, the insulating layer
13
and the source/drain electrodes
14
are formed to complete the semiconductor device
152
.
In buried-channel MOSFETs as exemplified by the semiconductor device
152
, the advances in miniaturization is incurring the problem that a current which cannot be controlled with the gate voltage is likely to flow in the buried channel region, which is called punch-through current. The punch-through can be effectively suppressed by increasing the impurity concentration in the punch-through stopper layer
4
or by forming a shallower counter doped layer
5
and increasing the impurity concentration thereof.
However, increasing the impurity concentration of the punch-through stopper layer
4
increases the threshold voltage, which leads to another problem of lower driving capability. Further, it is difficult to finally obtain a shallow counter doped layer
5
with higher impurity concentration, since the high-temperature thermal process for activating the source/drain layers
12
which is performed after the formation of the counter doped layer
5
diffuses the impurity in the counter doped layer
5
.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-described problems of the conventional art, and an object of the present invention is to provide a semiconductor device which has excellent resistance to punch-through and is suitable for miniaturization and a manufacturing method thereof.
According to a first aspect of the present invention, a semiconductor device comprises: a semiconductor substrate having a main surface and a trench selectively formed in the main surface, the semiconductor substrate comprising a first semiconductor layer of a first conductivity type formed under the
Kitazawa Masashi
Oda Hidekazu
Shiozawa Katsuomi
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