Static information storage and retrieval – Read/write circuit – Testing
Patent
1994-09-29
1995-12-19
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Testing
371 223, G11C 700, G01R 3128
Patent
active
054774934
ABSTRACT:
A boundary scan test circuit comprises a plurality of register cells correspondingly to external pins of a semiconductor device, the register cells being coupled together to form a shift register during a test operation mode. The register cells includes a first selector for selecting one of a parallel input data, serial input data and a code signal, a first register for latching the output of the first selector to output a serial data to be input to a succeeding register cell, a second register for latching the output of the first selector, a second selector for selecting the parallel data or the output of the second register to output parallel data. The code signal is determined based on corresponding one of bits of ID code of the semiconductor device. The ID code is output from the register cells without providing an ID code register, resulting in a simple construction of the register cells and a reduced chip area for the semiconductor device.
REFERENCES:
patent: 5220281 (1993-06-01), Matsuki
patent: 5260947 (1993-11-01), Posse
patent: 5260948 (1993-11-01), Simpson et al.
patent: 5260950 (1993-11-01), Simpson et al.
patent: 5341096 (1994-08-01), Yamamura
Dinh Son
NEC Corporation
Nelms David C.
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